Frequency selective surface designing device

Patent metadata

Field	Value
Publication number	US-11588248-B2
Application number	US-201917289835-A
Country	US
Kind code	B2
Filing date	Oct 16, 2019
Priority date	Oct 30, 2018
Publication date	Feb 21, 2023
Grant date	Feb 21, 2023

Abstract

To accurately estimate frequency characteristics from structural parameters of a frequency selective surface. A frequency selective surface design apparatus includes an LC generation unit 20 that receives an input of a structural parameter, and generates an inductance L and a capacitance C of a unit cell, a corrected resonance point calculation unit 30 that receives the number n of times of calculation input from an outside, the inductance L, and the capacitance C, models a correction circuit by using a circuit in which a virtual capacitance is connected in parallel via a transmission line to each distribution inductance obtained by division of the inductance L by the calculation number n and the transmission line is terminated at the capacitance C, and calculates a corrected resonant frequency fC from the impedance of the correction circuit, and a characteristic calculation unit 40 that receives inputs of the inductance L, the capacitance C, and the corrected resonant frequency fC, calculates a pre-correction resonant frequency from the inductance L and the capacitance C, obtains a correction coefficient by dividing the corrected resonant frequency fC by the pre-correction resonant frequency, and calculates a corrected return loss and a corrected insertion loss.

First claim

The invention claimed is:

1. A frequency selective surface design apparatus comprising:
a frequency selective surface in which a unit cell of a resonator is arranged on a plane;
an LC generation unit, including one or more processors, configured to receive an input of a structural parameter representing a structure of the unit cell, and generate an inductance and a capacitance of the unit cell;
a corrected resonance point calculation unit, including one or more processors, configured to receive inputs of a number of times of calculation input from an outside, the inductance, and the capacitance, model a correction circuit by using a circuit in which a virtual capacitance is connected in parallel via a transmission line to each of distribution inductances obtained by division of the inductance by the number of times of calculation and the transmission line is terminated at the capacitance, and calculate a corrected resonant frequency from an impedance of the correction circuit in which the virtual capacitance causes a phase difference generated in the unit cell and a phase difference generated in the transmission line to match with each other; and
a characteristic calculation unit, including one or more processors, configured to receive inputs of the inductance, the capacitance, and the corrected resonant frequency, calculate a pre-correction resonant frequency from the inductance and the capacitance, obtain a correction coefficient by dividing the corrected resonant frequency by the pre-correction resonant frequency, and calculate a corrected return loss and a corrected insertion loss by multiplying each of a pre-correction return loss and a pre-correction insertion loss by the correction coefficient.

2. The frequency selective surface design apparatus according to claim 1 , wherein
the unit cell includes a conductive pattern in which a first conductive pattern is formed in a cross shape on a dielectric substrate, a horizontal pattern and a vertical pattern forming the cross shape extend in each direction by a predetermined length, and at ends of the horizontal pattern and the vertical pattern extending by the predetermined length, second conductive patterns with a larger width than widths of the horizontal pattern and the vertical pattern extends by a predetermined length in both directions on the dielectric substrate orthogonal to each other are provided, and
the structural parameter specifies a shape of the conductive pattern.

3. The frequency selective surface design apparatus according to claim 1 , wherein
the distribution inductances are values obtained by equal division of the inductance by n which is the number of times of calculation,
the virtual capacitance is a value obtained from a phase matching condition for equalizing a unit phase difference of the transmission line and a phase difference generated in division of a half of a surface of the unit cell with respect to a center of the unit cell by the n, and
the corrected resonant frequency is a lowest one of a plurality of calculated resonant frequencies.

4. The frequency selective surface design apparatus according to claim 1 , wherein
the pre-correction resonant frequency is a resonant frequency of an LC series resonant circuit in which the inductance and the capacitance are connected in series.

5. The frequency selective surface design apparatus according to claim 1 , further comprising: a structural parameter resetting unit, including one or more processors, configured to receive inputs of the corrected return loss and the corrected insertion loss calculated by the characteristic calculation unit and a desired resonant frequency input from the outside, obtain a difference between the corrected resonant frequency and the desired resonant frequency, and perform structural-parameter resetting from the difference, wherein the structural parameter resetting unit is configured to repeat the structural-parameter resetting until the difference reaches a predetermined value.

Assignees

• Nippon Telegraph & Telephone

Inventors

• Itami Go
• Toriumi Yohei
• Kato Jun

Classifications

• H01Q15/141

  Apparatus or processes specially adapted for manufacturing reflecting surfaces · CPC title

• H01Q15/0046 Primary

  Theoretical analysis and design methods of such selective devices · CPC title

• H01Q15/002 Primary

  said selective devices being reconfigurable or tunable, e.g. using switches or diodes · CPC title

• G06F2119/14

  Force analysis or force optimisation, e.g. static or dynamic forces · CPC title

• G06F30/39

  Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347) · CPC title