High voltage blocking III-V semiconductor device

Patent metadata

Field	Value
Publication number	US-11588024-B2
Application number	US-201715462019-A
Country	US
Kind code	B2
Filing date	Mar 17, 2017
Priority date	Mar 17, 2017
Publication date	Feb 21, 2023
Grant date	Feb 21, 2023

Abstract

A semiconductor device includes a type IV semiconductor base substrate, a first type III-V semiconductor layer formed on a first surface of the base substrate, and a second type III-V semiconductor layer with a different bandgap as the first type III-V being formed on the first type III-V semiconductor layer. The semiconductor device further includes first and second electrically conductive device terminals each being formed on the second type III-V semiconductor layer and each being in ohmic contact with the two-dimensional charge carrier gas. The base substrate includes a first highly doped island that is disposed directly beneath the second device terminal and extends to the first surface of the base substrate. The first highly-doped island is laterally disposed between portions of semiconductor material having a lower net doping concentration than the first highly-doped island.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a base substrate comprising type IV semiconductor material;
a first semiconductor layer comprising type III-V semiconductor material and formed on a first surface of the base substrate;
a second semiconductor layer comprising type III-V semiconductor material and formed on the first semiconductor layer, the type III-V semiconductor material of the second semiconductor layer having a bandgap different from a bandgap of the type III-V semiconductor material of the first semiconductor layer such that a two-dimensional charge carrier gas forms at an interface between the first semiconductor layer and the second semiconductor layer;
a first terminal formed on the second semiconductor layer and being in ohmic contact with the two-dimensional charge carrier gas; and
a second terminal formed on the second semiconductor layer and being in ohmic contact with the two-dimensional charge carrier gas,
wherein the base substrate comprises a first highly-doped island that is disposed directly beneath the second terminal and extends to the first surface of the base substrate, and
wherein the first highly-doped island is laterally disposed between portions of a semiconductor material, the portions of the semiconductor material having a net doping concentration lower than a net doping concentration of the first highly-doped island and being either the type IV semiconductor material from the base substrate or type III-V semiconductor material from a transition layer between the base substrate and the first semiconductor layer,
wherein the semiconductor device is configured to block a conductive connection between the first terminal and the second terminal during a blocking state,
wherein the semiconductor device is configured such that a depletion region extends from the second terminal and into the base substrate during the blocking state.

2. The semiconductor device of claim 1 , wherein the portions of the semiconductor material are portions of the base substrate that extend to the first surface, and
wherein the net doping concentration of the portions of the semiconductor material is an intrinsic doping concentration of the base substrate.

3. The semiconductor device of claim 2 , wherein the intrinsic doping concentration of the base substrate is in a range of 1×10 15 dopant atoms/cm 3 -1×10 19 dopant atoms/cm 3 , wherein the net doping concentration of the first highly-doped island is in a range of 1×10 19 dopant atoms/cm 3 -1×10 22 dopant atoms/cm 3 , and wherein the net doping concentration of the first highly-doped island is at least two orders of magnitude greater than the intrinsic doping concentration of the base substrate.

4. The semiconductor device of claim 2 , wherein the intrinsic doping concentration of the base substrate is at least 1×10 18 dopant atoms/cm 3 , and
wherein the net doping concentration of the first highly-doped island is at least two orders of magnitude greater than the intrinsic doping concentration of the base substrate.

5. The semiconductor device of claim 1 , wherein an intrinsic conductivity type of the base substrate is a first conductivity type, and wherein the first highly-doped island has a net conductivity type of a second conductivity type that is opposite from the first conductivity type.

6. The semiconductor device of claim 1 , wherein an intrinsic conductivity type of the base substrate is a first conductivity type, and wherein the first highly-doped island has a net conductivity type of the first conductivity type.

7. The semiconductor device of claim 1 , wherein the first highly-doped island is laterally disposed between portions of the transition layer.

8. The semiconductor device of claim 1 , wherein the semiconductor device is a high-electron-mobility-transistor, wherein the first terminal is a source terminal, and wherein the second terminal is a drain terminal.

9. The semiconductor device of claim 1 , wherein the semiconductor device is configured as a diode, wherein the first terminal is an anode, and wherein the second terminal is a cathode.

10. The semiconductor device of claim 1 , wherein the base substrate further comprises second and third highly-doped islands that are laterally disposed between additional portions of the semiconductor material, the additional portions of the semiconductor material each having a net doping concentration lower than a net doping concentration of each of the second and third highly-doped islands.

11. The semiconductor device of claim 1 , wherein the base substrate is a silicon substrate, wherein the first semiconductor layer is a layer of gallium nitride, and wherein the second semiconductor layer is a layer of aluminum gallium nitride.

12. The semiconductor device of claim 1 , wherein an underside of the second terminal faces the base substrate and is in ohmic contact with the two-dimensional charge carrier gas, and wherein the first highly-doped island is disposed directly beneath the underside of the second terminal.

13. The semiconductor device of claim 1 , wherein the second terminal is isolated from the base substrate.

14. A semiconductor device, comprising:
a base substrate comprising a type IV semiconductor material and a highly-doped island that extends to a first surface of the base substrate and is laterally disposed between portions of a semiconductor material, the portions of the semiconductor material having a net doping concentration lower than a net doping concentration of the first highly-doped island and being either type IV semiconductor material from the base substrate or type III-V semiconductor material from a transition layer formed on the base substrate;
a first semiconductor layer comprising III-V semiconductor material and disposed on the transition layer;
a second semiconductor layer comprising type III-V semiconductor material and formed on the first semiconductor layer, the type III-V semiconductor material of the second semiconductor layer having a bandgap different from a bandgap of the type III-V semiconductor material of the first semiconductor layer such that a two-dimensional charge carrier gas forms at an interface between the first semiconductor layer and the second semiconductor layer;
a first terminal formed on the second semiconductor layer and being in ohmic contact with the two-dimensional charge carrier gas; and
a second terminal formed on the second semiconductor layer and being in ohmic contact with the two-dimensional charge carrier gas,
wherein the semiconductor device is configured to block a conductive connection between the first terminal and the second terminal during a blocking state,
wherein a depletion region extending from the second terminal and into the base substrate forms across the highly-doped island during the blocking state, and
wherein the highly-doped island is configured to suppress electron generation in the depletion region via impact ionization during the blocking state.

15. The semiconductor device of claim 14 , wherein the semiconductor device is a high-electron-mobility-transistor, wherein the first terminal is a source terminal, wherein the second terminal is a drain terminal, and wherein the highly-doped island is disposed directly beneath the drain terminal.

16. The semiconductor device of claim 14 , wherein the semiconductor device is a diode, wherein the first terminal is an anode terminal, wherein the second terminal is a cathode terminal, and wherein the highly-doped island is disposed directly beneath the cathode terminal.

Assignees

• Infineon Technologies Austria Ag

Inventors

• Yang Shu
• Longobardi Giorgia
• Udrea Florin
• Pagnano Dario
• Camuso Gianluca
• Sun Jinming
• Imam Mohamed
• Charles Alain

Classifications

• H10D62/8503

  Nitride Group III-V materials, e.g. AlN or GaN · CPC title

• H10D64/256

  for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673) · CPC title

• H10D62/10

  Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies · CPC title

• H10D30/475

  having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs · CPC title

• H10D8/00

  Diodes (variable-capacitance diodes H10D1/64; gated diodes H10D12/00) · CPC title