System and method for polling-based storage command processing

Patent metadata

Field	Value
Publication number	US-11586569-B2
Application number	US-202117383604-A
Country	US
Kind code	B2
Filing date	Jul 23, 2021
Priority date	Jul 23, 2021
Publication date	Feb 21, 2023
Grant date	Feb 21, 2023

Abstract

A method, computer program product, and computing system for assigning a first set of interrupts for exclusive processing by a first set of central processing units (CPU) cores. A second set of interrupts may be assigned for processing by a second set of CPU cores. The first set of interrupts may be processed using the first set of CPU cores. The second set of interrupts may be converted to a set of polling operations, thus defining a set of converted polling operations. The set of converted polling operations may be processed using the second set of CPU cores.

First claim

What is claimed is:

1. A computer-implemented method, executed on a computing device, comprising:
assigning a first set of interrupts for exclusive processing by a first set of central processing units (CPU) cores;
assigning a second set of interrupts for processing by a second set of CPU cores;
processing the first set of interrupts using the first set of CPU cores;
converting the second set of interrupts to a set of polling operations, thus defining a set of converted polling operations; and
processing the set of converted polling operations using the second set of CPU cores.

2. The computer-implemented method of claim 1 , wherein converting the second set of interrupts to a set of polling operations includes:
preventing the second set of interrupts from being processed as interrupts; and
storing each interrupt of the second set of interrupts as a polling operation on one or more buffers.

3. The computer-implemented method of claim 2 , wherein processing the set of converted polling operations using the second set of CPU cores includes polling the set of converted polling operations from the one or more buffers using the second set of CPU cores.

4. The computer-implemented method of claim 1 , wherein the first set of interrupts and the second set of interrupts include one or more interrupts associated with Fibre Channel protocol transport layer.

5. The computer-implemented method of claim 4 , wherein the first set of interrupts include one or more IO command interrupts.

6. The computer-implemented method of claim 5 , further comprising:
determining, using the one or more IO command interrupts, whether an IO command interrupt is associated with a read command or a write command;
in response to determining that the IO command interrupt is associated with a read command, converting the read command interrupt to a polling operation; and
in response to determining that the IO command interrupt is associated with a write command, processing the write command interrupt using the first set of CPU cores.

7. The computer-implemented method of claim 4 , wherein the second set of interrupts include at least one of:
one or more backend submission command interrupts; and
one or more transaction completion interrupts.

8. A computer program product residing on a non-transitory computer readable medium having a plurality of instructions stored thereon which, when executed by a processor, cause the processor to perform operations comprising:
assigning a first set of interrupts for exclusive processing by a first set of central processing units (CPU) cores;
assigning a second set of interrupts for processing by a second set of CPU cores;
processing the first set of interrupts using the first set of CPU cores;
converting the second set of interrupts to a set of polling operations, thus defining a set of converted polling operations; and
processing the set of converted polling operations using the second set of CPU cores.

9. The computer program product of claim 8 , wherein converting the second set of interrupts to a set of polling operations includes:
preventing the second set of interrupts from being processed as interrupts; and
storing each interrupt of the second set of interrupts as a polling operation on one or more buffers.

10. The computer program product of claim 9 , wherein processing the set of converted polling operations using the second set of CPU cores includes polling the set of converted polling operations from the one or more buffers using the second set of CPU cores.

11. The computer program product of claim 8 , wherein the first set of interrupts and the second set of interrupts include one or more interrupts associated with Fibre Channel protocol transport layer.

12. The computer program product of claim 11 , wherein the first set of interrupts include one or more IO command interrupts.

13. The computer program product of claim 12 , wherein the operations further comprise:
determining, using the one or more IO command interrupts, whether an IO command interrupt is associated with a read command or a write command;
in response to determining that the IO command interrupt is associated with a read command, converting the read command interrupt to a polling operation; and
in response to determining that the IO command interrupt is associated with a write command, processing the write command interrupt using the first set of CPU cores.

14. The computer program product of claim 11 , wherein the second set of interrupts include at least one of:
one or more backend submission command interrupts; and
one or more transaction completion interrupts.

15. A computing system comprising:
a memory; and
a processor configured to assign a first set of interrupts for exclusive processing by a first set of central processing units (CPU) cores, wherein the processor is further configured to assign a second set of interrupts for processing by a second set of CPU cores, wherein the processor is further configured to process the first set of interrupts using the first set of CPU cores, wherein the processor is further configured to convert the second set of interrupts to a set of polling operations, thus defining a set of converted polling operations, and wherein the processor is further configured to process the set of converted polling operations using the second set of CPU cores.

16. The computing system of claim 15 , wherein converting the second set of interrupts to a set of polling operations includes:
preventing the second set of interrupts from being processed as interrupts; and
storing each interrupt of the second set of interrupts as a polling operation on one or more buffers.

17. The computing system of claim 16 , wherein processing the set of converted polling operations using the second set of CPU cores includes polling the set of converted polling operations from the one or more buffers using the second set of CPU cores.

18. The computing system of claim 15 , wherein the first set of interrupts and the second set of interrupts include one or more interrupts associated with Fibre Channel protocol transport layer.

19. The computing system of claim 18 , wherein the first set of interrupts include one or more IO command interrupts.

20. The computing system of claim 18 , wherein the second set of interrupts include at least one of:
one or more backend submission command interrupts; and
one or more transaction completion interrupts.

Assignees

• Emc Ip Holding Co Llc

Inventors

• Ravich Leonid
• Zinger Eldad
• Engel Amit

Classifications

• G06F13/24 Primary

  using interrupt (G06F13/32 takes precedence) · CPC title

• G06F13/102

  where the program performs an interfacing function, e.g. device driver (G06F13/105 takes precedence; contention policies within device drivers G06F9/4881; scheduling within device drivers G06F9/52) · CPC title