Data prefetching method and terminal device

Patent metadata

Field	Value
Publication number	US-11586544-B2
Application number	US-201917263197-A
Country	US
Kind code	B2
Filing date	Jul 23, 2019
Priority date	Jul 27, 2018
Publication date	Feb 21, 2023
Grant date	Feb 21, 2023

Abstract

A data prefetching method and a terminal device are provided. The CPU core cluster is configured to deliver a data access request to a first cache of the at least one level of cache, where the data access request carries a first address, and the first address is an address of data that the CPU core cluster currently needs to access in the memory. The prefetcher in the terminal device provided in embodiments of this application may generate a prefetch-from address, and load data corresponding to the generated prefetch-from address to the first cache. When needing to access the data, the CPU core cluster can read from the first cache, without a need to read from the memory. This helps increase an operating rate of the CPU core cluster.

First claim

What is claimed is:

1. A terminal device, comprising:
a CPU core cluster;
at least one level of cache;
a prefetcher; and
a memory, wherein
the CPU core cluster is configured to deliver a data access request to a first cache of the at least one level of cache, wherein the data access request carries a first address, and the first address is an address of data that the CPU core cluster currently needs to access in the memory; and
the prefetcher is configured to:
generate a first address offset based on a first prefetching algorithm and an address carried in a historical data access request;
generate a first prefetch-from address based on the first address offset and the first address; and
load, from the memory to the first cache based on the first prefetch-from address, data corresponding to the first prefetch-from address.

2. The terminal device according to claim 1 , wherein the first cache is a last level cache of the at least one level of cache.

3. The terminal device according to claim 1 , wherein
the at least one level of cache comprises two levels of cache, and the first cache is a level 2 cache of the two levels of cache; and
the CPU core cluster being configured to deliver the data access request to the first cache comprises:
the CPU core cluster being configured to deliver the data access request to a level 1 cache of the two levels of cache, wherein a cache controller of the level 1 cache is configured to send the data access request to the level 2 cache when determining that the data corresponding to the first address does not exist in the level 1 cache; or

the CPU core cluster being configured to deliver the data access request to the first cache comprises:
the CPU core cluster being configured to deliver the data access request to a level 1 cache of the two levels of cache, wherein the cache controller of the level 1 cacheb is configured to feed back response information to the CPU core cluster when determining that the data corresponding to the first address does not exist in the level 1 cache; and
the CPU core cluster delivers the data access request to the level 2 cache of the two levels of cache after receiving the response information.

4. The terminal device according to claim 1 , wherein the prefetcher is configured to store a plurality of prefetching algorithms, and the prefetcher is configured to determine the first prefetching algorithm from the plurality of prefetching algorithms based on an application program currently running on the terminal device.

5. The terminal device according to claim 1 , wherein the prefetcher is configured to determine the first prefetching algorithm based on a hit rate or a miss rate during data prefetching, wherein the hit rate is a ratio of data that is of prefetched data and that is accessed by the CPU core cluster to the prefetched data, and the miss rate is a ratio of data that is of the prefetched data and that is not accessed by the CPU core cluster to the prefetched data.

6. The terminal device according to claim 1 , wherein
the prefetcher includes N prefetching algorithms,
each prefetching algorithm takes effect in one period, and
the prefetcher is further configured to:
perform data prefetching in each of N periods based on a prefetching algorithm that takes effect in the period;
determine a first hit rate of data prefetching performed based on the prefetching algorithm that takes effect in each of the N periods, to obtain N first hit rates; and
determine a highest first hit rate of the N first hit rates, and determine that a prefetching algorithm corresponding to the highest first hit rate is the first prefetching algorithm, wherein

the first hit rate is a ratio, to the prefetched data, of data that is of the prefetched data and that is accessed by the CPU core cluster after the prefetched data is stored to the first cache by the prefetcher based on the prefetching algorithm that takes effect in the period.

7. The terminal device according to claim 1 , wherein the memory is a double data rate synchronous dynamic random access memory (DDR SDRAM).

8. The terminal device according to claim 1 , wherein
the at least one level of cache comprises three levels of cache; and
the CPU core cluster being configured to deliver the data access request to the first cache comprises:
the CPU core cluster being configured to deliver the data access request to a level 1 cache of the three levels of cache, wherein a cache controller of the level 1 cache is configured to send the data access request to the level 2 cache when determining that the data corresponding to the first address does not exist in the level 1 cache; and
a cache controller of the level 2 cache being configured to send the data access request to the level 3 cache when determining that the data corresponding to the first address does not exist in the level 2 cache; or
the CPU core cluster being configured to deliver the data access request to the first cache comprises:
the CPU core cluster being configured to deliver the data access request to a level 1 cache of the three levels of cache, wherein the cache controller of the level 1 cache is configured to send the data access request to the level 2 cache when determining that the data corresponding to the first address does not exist in the level 1 cache;
the cache controller of the level 2 cache being configured to feedback response information to the CPU core cluster when determining that the data corresponding to the first address does not exist in the level 2 cache; and
the CPU core cluster being further configured to deliver the data access request to the level 3 cache of the three levels of cache after receiving the response information.

9. A data prefetching method, comprising:
delivering a data access request to a first cache of at least one level of cache, wherein the data access request carries a first address, and the first address is an address of data that a CPU core cluster currently needs to access in a memory;
generating a first address offset based on a first prefetching algorithm and an address carried in a historical data access request
generating a first prefetch-from address based on the first address offset and the first address; and
loading, from the memory to the first cache based on the first prefetch-from address, data corresponding to the first prefetch-from address.

10. The method according to claim 9 , wherein the first cache is a last level cache of the at least one level of cache.

11. The method according to claim 9 , wherein
if the at least one level of cache comprises two levels of cache, the first cache is a level 2 cache in the two levels of cache; and
the delivering the data access request to the first cache comprises:
delivering the data access request to a level 1 cache of the two levels of cache, wherein a cache controller of the level 1 cache is configured to send the data access request to the level 2 cache when determining that the data corresponding to the first address does not exist in the level 1 cache; or

the delivering the data access request to the first cache comprises:
delivering the data access request to the level 1 cache of the two levels of cache, wherein the cache controller of the level 1 cache is configured to generate response information when determining that the data corresponding to the first address does not exist in the level 1 cache; and
delivering the data access request to the level 2 cache of the two levels of cache based on the response information.

12. The method according to claim 9 , wherein before generating the first prefetch-from address, the method further comprises:
determining the f

Assignees

• Huawei Tech Co Ltd

Inventors

• Shi Gongzheng
• Ma Jianliang
• Wang Liqiang

Classifications

• G06F12/0877 Primary

  Cache access modes · CPC title

• G06F12/0862 Primary

  with prefetch · CPC title

• G06F2212/1021

  Hit rate improvement · CPC title

• G06F2212/602

  Details relating to cache prefetching · CPC title

• G06F12/0811

  with multilevel cache hierarchies · CPC title