Systems for introducing memristor random telegraph noise in Hopfield neural networks

Patent metadata

Field	Value
Publication number	US-11580411-B2
Application number	US-201816224145-A
Country	US
Kind code	B2
Filing date	Dec 18, 2018
Priority date	Dec 18, 2018
Publication date	Feb 14, 2023
Grant date	Feb 14, 2023

Abstract

Systems are provided for implementing a hardware accelerator. The hardware accelerator emulate a stochastic neural network, and includes a first memristor crossbar array, and a second memristor crossbar array. The first memristor crossbar array can be programmed to calculate node values of the neural network. The nodes values can be calculated in accordance with rules to reduce an energy function associated with the neural network. The second memristor crossbar array is coupled to the first memristor crossbar array and programmed to introduce noise signals into the neural network. The noise signals can be introduced such that the energy function associated with the neural network converges towards a global minimum and modifies the calculated node values.

First claim

What is claimed is:

1. A hardware accelerator, comprising:
a first memristor crossbar array programmed to calculate node values of a neural network, wherein the nodes values are calculated in accordance with rules to reduce an energy function associated with the neural network, the first memristor crossbar array comprising:
a plurality of first weight lines,
a plurality of second weight lines, and
a plurality of memory cells, wherein each of the plurality of memory cells is coupled across an intersection of one of the plurality of first weight lines and one of the plurality of second weight lines; and
a second memristor crossbar array coupled to the first memristor crossbar array and programmed to introduce noise signals into the neural network, wherein the noise signals are introduced such that the energy function associated with the neural network converges towards a global minimum and modifies the calculated node values, the second crossbar array comprising:
a first noise line;
a plurality of second noise lines, wherein a number of the plurality of second lines is equal to a number of the plurality of first weighted lines for the first crossbar array such that each of the plurality of second noise lines is connected to one of the plurality of first weighted lines for the first crossbar array; and
a plurality of noise memory cells, wherein each of the plurality of noise memory cells are coupled across an intersection of the first noise line and one of the plurality of second noise lines.

2. The hardware accelerator of claim 1 , wherein:
the second plurality of weight lines is a plurality of weight row lines;
the second plurality of weight lines is a plurality of weight column lines; and
wherein the plurality of memory cells are programmed according to a weight matrix to output a calculated node value of the neural network across each of the plurality of weight column lines.

3. The hardware accelerator of claim 1 , wherein:
the first noise line is a noise row line;
the plurality of second noise lines is a plurality of noise column lines; and
each of the plurality of noise memory cells is coupled across an intersection of the noise row line and one of the plurality of noise column lines.

4. The hardware accelerator of claim 1 , wherein each of the plurality of noise memory cells are tunable to output a noise signal having a fluctuating current across the noise column line.

5. The hardware accelerator of claim 4 , wherein the first noise line receives a controlled input voltage that tunes a conductance value for each of the plurality of noise memory cells to output the noise signal.

6. The hardware accelerator of claim 5 , wherein the noise signals are generated in accordance with random telegraph noise such that the calculated node values output by the first memristor crossbar array are modified.

7. The hardware accelerator of claim 5 , wherein the second memristor crossbar array outputs the noise signals in parallel with the output of the calculated node values from the first memristor crossbar array.

8. The hardware accelerator of claim 1 , wherein each of the noise memory cells comprise a memristor.

9. The hardware accelerator of claim 1 , wherein the modified calculated node values correspond to a solution of a computational problem mapped to the neural network.

10. The hardware accelerator of claim 9 , wherein the neural network is emulated by the hardware accelerator.

11. The hardware accelerator of claim 1 , wherein the neural network comprises a Hopfield Neural Network (HNN).

12. A hardware accelerator, comprising:
a first memristor crossbar array programmed to calculate node values of a neural network, wherein the nodes values are calculated in accordance with rules to reduce an energy function associated with the neural network, and wherein the first memristor crossbar array comprises:
a plurality of weight row lines;
a plurality of weight column lines; and
a plurality of memory cells, wherein each of the plurality of memory cells are coupled across an intersection of one the plurality of weight row lines and one of the plurality of weight column lines and programmed according to a weight matrix to output a calculated node value of the neural network across each of the plurality of weight column lines; and

a second memristor crossbar array coupled to the first memristor crossbar array and programmed to introduce noise signals into the neural network, wherein the noise signals are introduced such that the energy function associated with the neural network converges towards a global minimum and modifies the calculated node values, and wherein the second memristor crossbar array comprises:
a plurality of noise row lines, wherein a number of the plurality of noise row lines is equal to a number of the plurality of weighted row lines for the first memristor crossbar array such that each of the plurality of noise row lines is connected to one of the plurality of weighted row lines for the first memristor crossbar array;
a noise column line; and
a plurality of noise memory cells, wherein each of the plurality of noise memory cells are coupled across an intersection of the noise row line and one of the plurality of noise column lines.

13. The hardware accelerator of claim 12 , wherein the plurality of noise memory cells comprises memristors and the neural network comprises a Hopfield Neural Network (HNN).

14. The hardware accelerator of claim 13 , wherein a conductance of each of the memristors is tunable to output a noise signal having a fluctuating current across the noise row lines.

15. The hardware accelerator of claim 14 , wherein the noise signals are generated in accordance with random telegraph noise (RTN) such that the calculated node values output by the first memristor crossbar array are modified.

16. The hardware accelerator of claim 15 , wherein the first memristor crossbar array outputs currents representing a dot-product computation based on the weight matrix to calculate the node value of the neural network.

17. The hardware accelerator of claim 16 , wherein the modified node values are updated in accordance with an update rule to generate new inputs values into the neural network for a calculation of new node values.

18. The hardware accelerator of claim 17 , comprising a controller is programmed to:
determine whether the new node values are final node values of the neural network; and
upon determining that the new node values are not final node values, mapping the new input values to input voltages to be received as input by the plurality of weighted row lines of the first memristor crossbar array.

19. The hardware accelerator of claim 18 , where the controller is further programmed to:
upon determining that the new node values are the final node values, the new node values correspond to a solution of a computational problem mapped to the neural network.

20. A hardware accelerator comprising:
a first memristor crossbar array programmed to calculate node values of a neural network, wherein the nodes values are calculated in accordance with rules to reduce an energy function associated with the neural network, wherein the first memristor crossbar array comprises:
a plurality of row lines;
a plurality of column lines, wherein the plurality of row lines and the plurality of column lines intersect to form a matrix of memory cells;
a plurality of memory cells, wherein each memory cell is coupled to each combination of a row line and a column line in the matrix and each

Assignees

• Hewlett Packard Entpr Dev Lp

Inventors

• Kumar Suhas
• Van Vaerenbergh Thomas
• Strachan John Paul

Classifications

• G06N3/042

  Knowledge-based neural networks; Logical representations of neural networks · CPC title

• G11C2213/77

  Array wherein the memory element being directly connected to the bit lines and word lines without any access device being used · CPC title

• G11C2213/79

  Array wherein the access device being a transistor · CPC title

• G11C13/0069

  Writing or programming circuits or methods · CPC title

• G06N3/044

  Recurrent networks, e.g. Hopfield networks · CPC title