Extended hold-off time for SPAD quench assistance

Patent metadata

Field	Value
Publication number	US-11579016-B2
Application number	US-202117392422-A
Country	US
Kind code	B2
Filing date	Aug 3, 2021
Priority date	Dec 12, 2019
Publication date	Feb 14, 2023
Grant date	Feb 14, 2023

Abstract

A single photon avalanche diode (SPAD) has a cathode coupled to a high voltage supply and an anode coupled to a first node. A photodetection circuit includes: a first n-channel transistor having a drain coupled to the first node, a source coupled to ground, and a gate coupled to a third node; a second n-channel transistor having a drain coupled to the first node, a source coupled to ground, and a gate coupled to a second node; and an inverter having an input coupled to the first node and an output coupled to an intermediate node. A current starved inverter has an input coupled to the intermediate node and an output coupled to the second node, a logic gate has inputs coupled to the intermediate node and the second node, and an output coupled to the third node.

First claim

The invention claimed is:

1. A photodetection circuit, comprising:
a single photon avalanche diode (SPAD) having a cathode coupled to a high voltage supply and an anode coupled to a first node;
a first n-channel transistor having a drain coupled to the first node, a source coupled to ground, and a gate coupled to a third node;
a second n-channel transistor having a drain coupled to the first node, a source coupled to ground, and a gate coupled to a second node;
an inverter having an input coupled to the first node and an output coupled to an intermediate node;
a current starved inverter having an input coupled to the intermediate node and an output coupled to the second node; and
a logic gate having inputs coupled to the intermediate node and the second node, and an output coupled to the third node.

2. The photodetection circuit of claim 1 , further comprising a third n-channel transistor having a drain directly electrically connected to the anode of the SPAD, a source directly electrically connected to the first node, and a gate coupled to an enable signal.

3. The photodetection circuit of claim 1 , wherein the inverter comprises:
a first p-channel transistor having a source coupled to a supply voltage, a drain coupled to the intermediate node, and a gate coupled to the first node; and
a fourth n-channel transistor having a drain coupled to the intermediate node, a source coupled to ground, and a gate coupled to the first node.

4. The photodetection circuit of claim 1 , wherein the current starved inverter comprises:
a second p-channel transistor having a source coupled to a supply voltage, a drain, and a gate coupled to a tuning voltage;
a third p-channel transistor having a source coupled to the drain of the second p-channel transistor, a drain coupled to the second node, and a gate coupled to the intermediate node; and
a fifth n-channel transistor having a drain coupled to the second node, a source coupled to ground, and a gate coupled to the intermediate node.

5. The photodetection circuit of claim 1 , further comprising a clamp diode having a cathode coupled to a SPAD turn-off signal and an anode coupled to the anode of the SPAD.

6. The photodetection circuit of claim 1 , wherein the SPAD is fully depleted.

7. A photodetection circuit, comprising:
a single photon avalanche diode (SPAD) having a first terminal coupled to a voltage supply, and second terminal coupled to a first node;
a first transistor having a first conduction terminal coupled to the first node, and a control terminal coupled to output from a combinational logic circuit;
a second transistor having a first conduction terminal coupled to the first conduction terminal of the first transistor and a control terminal coupled to a third node;
an inverter having an input coupled to the first conduction terminal of the first transistor, and an output coupled to an intermediate node; and
a starved inverter having an input coupled to the intermediate node and an output coupled to the third node.

8. The photodetection circuit of claim 7 , further comprising an enable transistor having a first conduction terminal coupled to the first node, a second conduction terminal coupled to the first conduction terminal of the first transistor, and a control terminal coupled to receive an enable signal.

9. The photodetection circuit of claim 7 , wherein the first terminal of the SPAD is a cathode and the second terminal of the SPAD is an anode.

10. The photodetection circuit of claim 7 , wherein the voltage supply is a high voltage supply.

11. The photodetection circuit of claim 7 , wherein the first transistor has a second conduction terminal coupled to a second voltage supply.

12. The photodetection circuit of claim 11 , wherein the second voltage supply is a reference voltage supply.

13. The photodetection circuit of claim 7 , wherein the starved inverter is starved of current by a current limiting device.

14. The photodetection circuit of claim 7 , wherein the combinational logic circuit comprises a logic gate having a first input coupled to the intermediate node, a second input coupled to the third node, and an output coupled to the control terminal of the first transistor.

15. The photodetection circuit of claim 7 , wherein the SPAD is fully depleted.

Assignees

• St Microelectronics Res & Dev Ltd

Inventors

• Al-Rawhani Mohammed
• Rae Bruce

Classifications

• G01J2001/442

  Single-photon detection or photon counting · CPC title

• G01J2001/4466

  Avalanche · CPC title

• G01J1/44 Primary

  Electric circuits {(for command of an exposure part G03B7/02)} · CPC title