Dynamic load balancing for multi-core computing environments

Patent metadata

Field	Value
Publication number	US-11575607-B2
Application number	US-202017018809-A
Country	US
Kind code	B2
Filing date	Sep 11, 2020
Priority date	Sep 11, 2019
Publication date	Feb 7, 2023
Grant date	Feb 7, 2023

Abstract

Methods, apparatus, systems, and articles of manufacture are disclosed for dynamic load balancing for multi-core computing environments. An example apparatus includes a first and a plurality of second cores of a processor, and circuitry in a die of the processor separate from the first and the second cores, the circuitry to enqueue identifiers in one or more queues in the circuitry associated with respective ones of data packets of a packet flow, allocate one or more of the second cores to dequeue first ones of the identifiers in response to a throughput parameter of the first core not satisfying a throughput threshold to cause the one or more of the second cores to execute one or more operations on first ones of the data packets, and provide the first ones to one or more data consumers to distribute the first data packets.

First claim

What is claimed is:

1. An apparatus for dynamic load balancing in a multi-core computing environment, the apparatus comprising:
a first core and a plurality of second cores of a processor; and
circuitry in a die of the processor, the circuitry separate from the first core and the second cores, the circuitry to:
enqueue identifiers in one or more queues in the circuitry, the identifiers associated with respective ones of data packets of a packet flow;
allocate one or more of the second cores to dequeue first ones of the identifiers in response to a throughput parameter of the first core not satisfying a throughput threshold to cause the one or more of the second cores to execute one or more operations on first ones of the data packets, the first ones of the data packets corresponding to the dequeued first ones of the identifiers; and
provide the first ones of the identifiers to one or more data consumers of the processor to distribute the first ones of the data packets.

2. The apparatus of claim 1 , wherein the circuitry is to:
allocate at least one of the first core or the one or more second cores of the processor to dequeue second ones of the identifiers in response to the throughput parameter not satisfying a throughput threshold to cause the at least one of the first core or the one or more second cores to execute one or more operations on second ones of the data packets, the second ones of the data packets corresponding to the dequeued second ones of the identifiers; and
provide the second ones of the identifiers to the one or more data consumers of the processor to distribute the second ones of the data packets.

3. The apparatus of claim 1 , wherein the data packets are first data packets, the packet flow is a first packet flow, the identifiers are first identifiers, the one or more operations are a first one or more operations, and the circuitry is to:
enqueue second identifiers in the one or more queues, the second identifiers associated with respective ones of second data packets of a second packet flow, the second packet flow different from the first packet flow;
allocate at least one of the first core or the one or more second cores to dequeue ones of the second identifiers to cause the at least one of the first core or the one or more second cores to execute second one or more operations on the second data packets, the second data packets corresponding to the dequeued ones of the second identifiers; and
provide the second identifiers to the one or more data consumers to distribute the second data packets.

4. The apparatus of claim 3 , wherein the first identifiers are atomic queue identifiers and the second identifiers are at least one of non-atomic queue identifiers or direct queue identifiers.

5. The apparatus of claim 1 , wherein the first core is a data producer, the data producer is to receive the data packets from a network interface in communication with a first network, and the one or more data consumers are to transmit the data packets to the network interface for distribution to a second network.

6. The apparatus of claim 1 , wherein the throughput parameter has a first value based on first telemetry data associated with the first core, the one or more second cores include a third core, and the circuitry is to:
allocate the third core to dequeue a first set of the first ones of the identifiers in response to the first value not satisfying the throughput threshold;
determine a second value of the throughput parameter in response to the allocation of the third core, the second value based on second telemetry data associated with at least one of the first core or the third core; and
dequeue a second set of the first ones of the identifiers to the first core and the third core in response to the second value satisfying the throughput threshold.

7. The apparatus of claim 6 , wherein the data packets are first data packets, the packet flow is a first packet flow, the identifiers are first identifiers, and the circuitry is to allocate one or more of second ones of the second cores to dequeue ones of second identifiers associated with second data packets of a second data flow different from the first packet flow, the second ones of the second cores not including the first core and the third core.

8. The apparatus of claim 1 , wherein the packet flow is an elephant flow based on a determination that the packet flow is a single session associated with a network connection that runs for a time period that satisfies a threshold.

9. The apparatus of claim 1 , wherein the packet flow is an elephant flow based on a determination that a bandwidth associated with the processor decreases below a threshold.

10. The apparatus of claim 1 , wherein the packet flow is an elephant flow based on a determination that the packet flow has a number of bytes that satisfies a threshold.

11. A method for dynamic load balancing in a multi-core computing environment, the method comprising:
enqueueing identifiers in one or more queues in circuitry of a processor, the identifiers associated with respective ones of data packets of a packet flow, the circuitry separate from a first core of the processor;
allocating one or more second cores of the processor to dequeue first ones of the identifiers in response to a throughput parameter of the first core not satisfying a throughput threshold;
executing, with the one or more of the second cores, one or more operations on first ones of the data packets corresponding to the dequeued first ones of the identifiers; and
providing the first ones of the identifiers to one or more data consumers of the processor to distribute the first ones of the data packets.

12. The method of claim 11 , further including:
allocating at least one of the first core or the one or more second cores of the processor to dequeue second ones of the identifiers in response to the throughput parameter not satisfying a throughput threshold;
executing the one or more operations on second ones of the data packets corresponding to the dequeued second ones of the identifiers with the at least one of the first core or the one or more of the second cores; and
providing the second ones of the identifiers to the one or more data consumers of the processor to distribute the second ones of the data packets.

13. The method of claim 11 , wherein the data packets are first data packets, the packet flow is a first packet flow, the identifiers are first identifiers, the one or more operations are a first one or more operations, and further including:
enqueueing second identifiers in the one or more queues in the circuitry, the second identifiers associated with respective ones of second data packets of a second packet flow, the second packet flow different from the first packet flow;
identifying at least one of the first core or the one or more second cores to dequeue ones of the second identifiers;
executing second one or more operations on the second data packets corresponding to the dequeued ones of the second identifiers with the at least one of the first core or the one or more of the second cores; and
providing the second identifiers to the one or more data consumers to distribute the second data packets.

14. The method of claim 13 , wherein the first identifiers are atomic queue identifiers and the second identifiers are at least one of non-atomic queue identifiers or direct queue identifiers.

15. The method of claim 11 , wherein the first core is a data producer, and further including:
receiving the data packets from a first network with a network interface in communication with the processor;
provi

Assignees

• Intel Corp

Inventors

• Palermo Stephen
• Chaddick Bradley
• Eads Gage
• Ganguli Mrittika
• Khade Abhishek
• Layek Abhirupa
• Maini Sarita
• Mcdonnell Niall
• Shah Rahul
• Shah Shrikant
• Burroughs William
• Sonnier David

Classifications

• H04L47/125 Primary

  by balancing the load, e.g. traffic engineering · CPC title

• H04L47/6275

  based on priority · CPC title

• H04L47/62

  characterised by scheduling criteria · CPC title

• H04L47/6255

  queue load conditions, e.g. longest queue first · CPC title

• H04L47/624

  Altering the ordering of packets in an individual queue · CPC title