Multi-standard low-density parity check decoder

Patent metadata

Field	Value
Publication number	US-11575389-B2
Application number	US-202017114865-A
Country	US
Kind code	B2
Filing date	Dec 8, 2020
Priority date	Dec 8, 2020
Publication date	Feb 7, 2023
Grant date	Feb 7, 2023

Abstract

A wireless receiving device comprises a low-density parity check (LDPC) decoding circuit, comprising a circular shifter constructed and arranged to simultaneously process multiple code words of a parity check matrix configured for different wireless communication standards, including performing a cyclic shift operation of the multiple code words to align with one or more requisite check nodes of a decoder and a logic circuit at an output of the circular shifter constructed and arranged for a matrix larger than the parity check matrix and that includes components having excess hardware due to the construction and arrangement for the larger matrix to decode the multiple code words of the smaller parity check matrix for output to the one or more requisite check nodes.

First claim

What is claimed is:

1. A wireless receiving device, comprising:
a low-density parity check (LDPC) decoding circuit, comprising:
a circular shifter constructed and arranged to simultaneously process multiple code words of a parity check matrix configured for different wireless communication standards, including performing a cyclic shift operation of the multiple code words to align with one or more requisite check nodes of a decoder;
an intermediate memory; and
a logic circuit at an output of the circular shifter constructed and arranged for a matrix larger than the parity check matrix and that includes components having excess hardware due to the construction and arrangement for the larger matrix, wherein the logic circuit is configured to decode the multiple code words of the parity check matrix at a same time for output to the one or more requisite check nodes by being configured to:
perform at least one first calculation on the multiple code words to obtain intermediate results;
store the intermediate results in the intermediate memory; and
perform at least one second calculation on the intermediate results stored in the intermediate memory.

2. The wireless receiving device of claim 1 , wherein the excess hardware includes one or more of a data path, random access memory, and flip-flop storage that is reused to decode the multiple code words at a same time.

3. The wireless receiving device of claim 1 , further comprising at least one check node updating (CNU) processor that includes the circular shifter and at least one variable node updating (VNU) processor, wherein the at least one VNU processor is configured to obtain the intermediate results stored in the intermediate memory and perform the at least one second calculation on the intermediate results every clock cycle.

4. The wireless receiving device of claim 3 , wherein:
the logic circuit includes a minimum data generator unit configured to perform the at least one first calculation;
the at least one first calculation comprises identification of first and second minimum values across a row of the parity check matrix;
the intermediate results comprise current minimum values for the row of the parity check matrix;
the at least one CNU processor is further configured to store, in the intermediate memory, the intermediate results; and
the at least one VNU processor is further configured to process prior intermediate results comprising current minimum values corresponding to a row of the parity check matrix previously processed by the at least one CNU processor.

5. The wireless receiving device of claim 4 , wherein the intermediate memory stores current minimum values corresponding to two or more rows of the parity check matrix previously processed by the at least one CNU processor.

6. The wireless receiving device of claim 5 , wherein the intermediate memory includes one or more flip-flop circuits.

7. The wireless receiving device of claim 4 , wherein the circular shifter is configured to shift one row of intermediate results of the at least one CNU processor at a time, wherein the intermediate memory is configured to store intermediate results corresponding to two rows of the parity check matrix, and wherein the at least one VNU processor is configured to process a sub-matrix of the parity check matrix based on the intermediate results corresponding to the two rows of the parity check matrix.

8. The wireless receiving device of claim 1 , wherein the circular shifter is configured to shift the multiple code words at the same time.

9. The wireless receiving device of claim 1 , wherein the circular shifter is configured to shift a set of the multiple code words of the parity check matrix at a same time to the right by a predetermined number of positions in order to receive and process a next set of multiple code words of the parity check matrix.

10. A low-density parity check (LDPC) decoding circuit of a wireless device, comprising:
a variable node updating (VNU) processor;
a check node updating (CNU) processor configured to perform, at a same time and on multiple code words of a parity check matrix, at least one first calculation to obtain intermediate results; and
a matrix processing system, comprising:
a special-purpose memory apparatus that stores the intermediate results generated by the CNU processor and corresponding to at least a first row and a second row of the parity check matrix; and
a decoding processor that provides the intermediate results corresponding to the at least the first row and the second row of the parity check matrix to the VNU processor.

11. The LDPC decoding circuit of claim 10 , wherein at least one of the VNU processor, the CNU processor, and the matrix processing system includes additional circuits constructed and arranged for processing a matrix larger than the parity check matrix, wherein the additional circuits simultaneously process the multiple code words of a row of the parity check matrix.

12. The LDPC decoding circuit of claim 11 , wherein the additional circuits include one or more of a data path, random access memory, and flip-flop storage that is reused to decode the multiple code words.

13. The LDPC decoding circuit of claim 11 , wherein the matrix processing system further comprises a shifter that receives an output that operates on a sub-matrix every clock cycle.

14. The LDPC decoding circuit of claim 13 , wherein the shifter shifts one of the first and second rows at a time, wherein the special-purpose memory apparatus stores two results from each of the first and second rows, and wherein the VNU processor processes a sub-matrix of the parity check matrix from the intermediate results corresponding to the first and second rows.

15. The LDPC decoding circuit of claim 14 , wherein the memory includes one or more flip-flop circuits.

16. The LDPC decoding circuit of claim 13 , wherein the shifter shifts a set of the multiple code words of the parity check matrix at a time to the right by a predetermined number of positions to receive and process a next set of multiple code words of the parity check matrix.

17. The LDPC decoding circuit of claim 11 , wherein the CNU processor further comprises a minimum data generator unit configured to identify first and second minimum values corresponding to each of the first and second rows, wherein the first and second minimum values corresponding to each of the first and second rows comprise the intermediate results, wherein the matrix processing system is further configured to store the first and second minimum values for each row as the CNU processor updates a memory for each column of the parity check matrix, and wherein the VNU processor is further configured to process the stored first and second minimum values corresponding to a row previously completed by the CNU processor.

18. A method of operation of a low-density parity check (LDPC) decoder, comprising:
simultaneously processing, by a circular shifter, multiple code words of a parity check matrix configured for different wireless communication standards, including:
performing a cyclic shift operation of the multiple code words to align with one or more requisite check nodes;

processing, by excess hardware of the LDPC decoder constructed and arranged for a larger matrix than the parity check matrix, the multiple code words, including:
decoding the multiple code words of the parity check matrix for output to the one or more requisite check nodes;

performing, by the one or more requisite check nodes, at least one first calculation on the decoded mul

Assignees

• Nxp Usa Inc

Inventors

• Bahary Robert

Classifications

• H03M13/616

  Matrix operations, especially for generator matrices or check matrices, e.g. column or row permutations · CPC title

• H03M13/114

  Shuffled, staggered, layered or turbo decoding schedules · CPC title

• H03M13/116

  Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices · CPC title

• H03M13/6561

  Parallelized implementations · CPC title

• H03M13/1137

  Partly parallel processing, i.e. sub-blocks or sub-groups of nodes being processed in parallel · CPC title