Balanced current-source inverter

Patent metadata

Field	Value
Publication number	US-11575329-B1
Application number	US-202117463676-A
Country	US
Kind code	B1
Filing date	Sep 1, 2021
Priority date	Sep 1, 2021
Publication date	Feb 7, 2023
Grant date	Feb 7, 2023

Abstract

A switching circuit for a current source inverter includes a first inverter leg, a second inverter leg, and a controller. The first inverter leg includes a first reverse-voltage-blocking (RB) switch, a second RB switch, and a third RB switch that are connected in series between a first bus line and a second bus line. The second inverter leg includes a fourth RB switch, a fifth RB switch, and a sixth RB switch are connected in series between the first bus line and the second bus line. The controller is configured to control a switch between an on-state and an off-state for each RB switch. When in the on-state, a reverse voltage is blocked by a respective RB switch, and a current with a positive polarity is conducted through the respective RB switch. When in the off-state, a voltage and the current are blocked by the respective RB switch.

First claim

What is claimed is:

1. A switching circuit for a current source inverter comprising:
a first inverter leg comprising
a first reverse-voltage-blocking (RB) switch;
a second RB switch; and
a third RB switch, wherein the first RB switch, the second RB switch, and the third RB switch are connected in series between a first bus line and a second bus line;

a second inverter leg comprising
a fourth RB switch;
a fifth RB switch; and
a sixth RB switch, wherein the fourth RB switch, the fifth RB switch, and the sixth RB switch are connected in series between the first bus line and the second bus line; and

a controller configured to control a switch between an on-state and an off-state for each RB switch;
wherein, when in the on-state, a reverse voltage is blocked by a respective RB switch, and a current with a positive polarity is conducted through the respective RB switch,
wherein, when in the off-state, a voltage and the current are blocked by the respective RB switch.

2. The switching circuit of claim 1 , wherein each RB switch comprises:
a semiconductor switch comprising
a first terminal;
a second terminal; and
a third terminal, wherein, when the on-state signal is sent to the first terminal, a first current is conducted from the second terminal to the third terminal; and

a diode, wherein an anode of the diode is connected to the third terminal.

3. The switching circuit of claim 1 , further comprising:
a seventh RB switch connected between the first bus line and the second bus line,
wherein the controller is further configured to switch the seventh RB switch between the on-state and the off-state.

4. The switching circuit of claim 3 , wherein the seventh RB switch is controlled to enter the on-state for a predefined time period at a beginning of a switching period, wherein the seventh RB switch is controlled to enter the on-state for the predefined time period before an end of the switching period.

5. The switching circuit of claim 4 , wherein either the first RB switch, the third RB switch, and the fifth RB switch or the second RB switch, the fourth RB switch, and the sixth RB switch are controlled to enter the on-state from the beginning of the switching period to the end of the switching period based on an angle of a space vector.

6. The switching circuit of claim 1 , further comprising:
a third inverter leg comprising
a seventh RB switch;
an eighth RB switch; and
a ninth RB switch, wherein the seventh RB switch, the eighth RB switch, and the ninth RB switch are connected in series between the first bus line and the second bus line;

wherein the controller is further configured to switch the seventh RB switch, the eighth RB switch, and the ninth RB switch between the on-state and the off-state.

7. The switching circuit of claim 6 , wherein the controller selects a first switching state for the first inverter leg from a set of four switching states, wherein the set includes only four switching states, a second switching state for the second inverter leg from the set of four switching states, and a third switching state for the third inverter leg from the set of four switching states, wherein each selected switching state is unique relative to other selected switching states.

8. The switching circuit of claim 7 , wherein a first selectable switching state of the set of four switching states indicates that, unless all of the RB switches are controlled in the off-state, when the second RB switch is controlled in the off-state, the first RB switch and the third RB switch are in the on-state, or when the fifth RB switch is controlled in the off-state, the fourth RB switch and the sixth RB switch are in the on-state, or when the eighth RB switch is controlled in the off-state, the seventh RB switch and the ninth RB switch are in the on-state.

9. The switching circuit of claim 8 , wherein a second selectable switching state of the set of four switching states indicates that, when the second RB switch is controlled in the on-state, the first RB switch and the third RB switch are in the off-state, or when the fifth RB switch is controlled in the on-state, the fourth RB switch and the sixth RB switch are in the off-state, or when the eighth RB switch is controlled in the on-state, the seventh RB switch and the ninth RB switch are in the off-state.

10. The switching circuit of claim 9 , wherein a third selectable switching state of the set of four switching states indicates that the first RB switch, the second RB switch, the third RB switch, the fourth RB switch, the fifth RB switch, the sixth RB switch, the seventh RB switch, the eighth RB switch and the ninth RB switch are controlled to be simultaneously in the off-state.

11. The switching circuit of claim 10 , wherein a fourth selectable switching state of the set of four switching states indicates that the first RB switch, the second RB switch, the third RB switch, the fourth RB switch, the fifth RB switch, the sixth RB switch, the seventh RB switch, the eighth RB switch and the ninth RB switch are controlled to be simultaneously in the on-state,
wherein, when one of the first inverter leg, the second inverter leg, or the third inverter leg is controlled to be in the fourth selectable switching state, a remaining pair of the first inverter leg, the second inverter leg, and the third inverter leg is controlled to be simultaneously in the off-state.

12. The switching circuit of claim 11 , wherein, when any RB switch transitions from the on-state to the off-state or from the off-state to the on-state, the first RB switch, the second RB switch, the third RB switch, the fourth RB switch, the fifth RB switch, the sixth RB switch, the seventh RB switch, the eighth RB switch and the ninth RB switch are controlled to be simultaneously in the off-state for a predefined time period.

13. The switching circuit of claim 6 , further comprising:
a tenth RB switch connected between the first bus line and the second bus line,
wherein the controller is further configured to switch the tenth RB switch between the on-state and the off-state.

14. The switching circuit of claim 13 , wherein the controller selects a first switching state for the first inverter leg from a set of three switching states, wherein the set includes only three switching states, a second switching state for the second inverter leg from the set of three switching states and a third switching state for the third inverter leg from the set of three switching states, wherein each selected switching state is unique relative to other selected switching states.

15. The switching circuit of claim 14 , wherein a first selectable switching state of the set of three switching states indicates that, unless all of the RB switches are controlled in the off-state, when the second RB switch is controlled in the off-state, the first RB switch and the third RB switch are in the on-state, or when the fifth RB switch is controlled in the off-state, the fourth RB switch and the sixth RB switch are in the on-state, or when the eighth RB switch is controlled in the off-state, the seventh RB switch and the ninth RB switch are in the on-state.

16. The switching circuit of claim 15 , wherein a second selectable switching state of the set of three switching states indicates that, when the second RB switch is controlled in the on-state, the first RB switch and the third RB switch are in the off-state, or when the fifth RB switch is controlled in the on-state, the fourth RB switch and the sixth RB switch are in the off-state, or when the eighth RB switch is controlled in the on-state, the seventh RB swit

Assignees

• Wisconsin Alumni Res Found

Inventors

• Jahns Thomas Merlin
• Dai Hang
• Sarlioglu Bulent
• Torres Renato Amorim

Classifications

• H02M7/5395

  by pulse-width modulation · CPC title

• H02M7/5388

  with asymmetrical configuration of switches · CPC title

• H02M1/44

  Circuits or arrangements for compensating for electromagnetic interference in converters or inverters · CPC title

• H02P27/06

  using DC to AC converters or inverters (H02P27/05 takes precedence) · CPC title

• H02P5/74 Primary

  controlling two or more AC dynamo-electric motors (H02P5/46, H02P5/60 take precedence) · CPC title