Gate driver circuit and display device including the same

Patent metadata

Field	Value
Publication number	US-11574598-B2
Application number	US-202117504999-A
Country	US
Kind code	B2
Filing date	Oct 19, 2021
Priority date	Dec 31, 2020
Publication date	Feb 7, 2023
Grant date	Feb 7, 2023

Abstract

Disclosed are a gate driver circuit having a reduced size, and a display device including the same. The gate driver circuit includes a plurality of stage circuits. Each stage circuit supplies a gate signal to each of gate lines arranged in a display panel, and includes a M node, a Q node, a QH node, and a QB node. Each stage circuit includes a gate signal output module configured to operate based on a voltage level of the Q node or a voltage level of the QB node to output first to j-th gate signals based on first to j-th scan clock signals or a first low-potential voltage.

First claim

What is claimed is:

1. A gate driver circuit for a display device comprising: a plurality of stage circuits, wherein at least one stage circuit from the plurality of stage circuits supplies a gate signal to a gate line, the at least one stage circuit including: a plurality of nodes comprising a M node, a Q node, a QH node, and a QB node; a line selector configured to: charge the M node based on a front carry signal responsive to an input of a line sensing preparation signal; and charge the Q node to a first high-potential voltage level responsive to an input of a reset signal or discharge the Q node to a third low-potential voltage level responsive to an input of a panel on signal; a Q node controller configured to: charge the Q node to the first high-potential voltage level responsive to an input of the front carry signal; and discharge the Q node to the third low-potential voltage level responsive to an input of a rear carry signal; a Q node and QH node stabilizer configured to discharge each of the Q node and the QH node to the third low-potential voltage level responsive to the QB node being charged to a second high-potential voltage; an inverter configured to change a voltage level of the QB node based on a voltage level of the Q node; a QB node stabilizer configured to discharge the QB node to the third low-potential voltage level responsive to an input of the rear carry signal, an input of the reset signal, and a charged voltage of the M node; a carry signal output module configured to output a carry signal based on a carry clock signal or the third low-potential voltage and based on the voltage level of the Q node or the voltage level of the QB node; and a gate signal output module configured to output first to j-th gate signals based on first to j-th scan clock signals or a first low-potential voltage and based on the voltage level of the Q node or the voltage level of the QB node.

2. The gate driver circuit of claim 1 , wherein the gate signal output module is configured to sequentially output the first to j-th gate signals based on the first to j-th scan clock signals responsive to the voltage level of the Q node being at a high level.

3. The gate driver circuit of claim 1 , wherein the gate signal output module includes:
a pull-up transistor configured to turn on responsive to the voltage level of the Q node being at a high level and supply the first to j-th scan clock signals to an output node responsive to being turned on;
a pull-down transistor configured to turn on responsive to the voltage level of the QB node being at the high level and supply the first low-potential voltage to the output node responsive to being turned on; and
a boosting capacitor connected to and disposed between a gate electrode and a source electrode of the pull-up transistor.

4. The gate driver circuit of claim 3 , wherein the pull-down transistor is turned on responsive to the voltage level of the QB node being charged to the second high-potential voltage.

5. The gate driver circuit of claim 1 , wherein the Q node and QH node stabilizer includes a first transistor and a second transistor configured to be turned on responsive to the QB node being charged to the second high-potential voltage.

6. The gate driver circuit of claim 1 , wherein a magnitude of the second high-potential voltage is adjusted based on an operation time duration of the gate driver circuit.

7. The gate driver circuit of claim 6 , wherein the magnitude of the second high-potential voltage increases as the operation time duration of the gate driver circuit increases.

8. The gate driver circuit of claim 6 , wherein the magnitude of the second high-potential voltage is increased in proportion to the operation time duration of the gate driver circuit.

9. A display device comprising: a display panel including sub-pixels respectively disposed at intersections between gate lines and data lines; a gate driver circuit configured to supply a scan signal to each gate line from the gate lines; a data driver circuit configured to supply a data voltage to each data line from the data lines; and a timing controller configured to control an operation of each of the gate driver circuit and the data driver circuit, wherein the gate driver circuit includes a plurality of stage circuits, wherein at least one stage circuit from the plurality of stage circuits supplies a gate signal to a gate line from the gate lines, the at least one stage circuit including: a plurality of nodes including a M node, a Q node, a QH node, and a QB node, a line selector configured to: charge the M node based on a front carry signal responsive to an input of a line sensing preparation signal; and charge the Q node to a first high-potential voltage level responsive to an input of a reset signal or discharge the Q node to a third low-potential voltage level responsive to an input of a panel on signal; a Q node controller configured to: charge the Q node to the first high-potential voltage level responsive to an input of the front carry signal; and discharge the Q node to the third low-potential voltage level responsive to an input of a rear carry signal; a Q node and QH node stabilizer configured to discharge each of the Q node and the QH node to the third low-potential voltage level responsive to the QB node being charged to a second high-potential voltage; an inverter configured to change a voltage level of the QB node based on a voltage level of the Q node; a QB node stabilizer configured to discharge the QB node to the third low-potential voltage level responsive to an input of the rear carry signal, an input of the reset signal, and a charged voltage of the M node; a carry signal output module configured to output a carry signal based on a carry clock signal or the third low-potential voltage and based on the voltage level of the Q node or the voltage level of the QB node; and a gate signal output module configured to output first to j-th gate signals based on first to j-th scan clock signals or a first low-potential voltage and based on the voltage level of the Q node or the voltage level of the QB node.

10. The display device of claim 9 , wherein the gate signal output module is configured to sequentially output the first to j-th gate signals based on the first to j-th scan clock signals responsive to the voltage level of the Q node being at a high level.

11. The display device of claim 9 , wherein the gate signal output module includes:
a pull-up transistor configured to turn on responsive to the voltage level of the Q node being at a high level and supply the first to j-th scan clock signals to an output node responsive to being turned on;
a pull-down transistor configured to turn on responsive to the voltage level of the QB node being at the high level and supply the first low-potential voltage to the output node responsive to being turned on; and
a boosting capacitor connected to and disposed between a gate electrode and a source electrode of the pull-up transistor.

12. The display device of claim 11 , wherein the pull-down transistor is turned on responsive to the voltage level of the QB node being charged to the second high-potential voltage.

13. The display device of claim 9 , wherein the Q node and QH node stabilizer includes a first transistor and a second transistor configured to be turned on responsive to the QB node being charged to the second high-potential voltage.

14. The display device of claim 9 , wherein a magnitude of the second high-potential voltage is adjusted based on an operation time duration of the gate driver circuit.

15. The display device of claim 14 , wherein the magnitude of the se

Assignees

• Lg Display Co Ltd

Inventors

• Chang Minkyu
• Son Miyoung
• Shin Hongjae

Classifications

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G09G2310/061

  for resetting or blanking · CPC title

• G09G3/3275

  Details of drivers for data electrodes · CPC title

• G09G3/3266 Primary

  Details of drivers for scan electrodes · CPC title

• G09G3/3233

  with pixel circuitry controlling the current through the light-emitting element · CPC title