Shift register unit, shift register, display panel and driving method thereof

Patent metadata

Field	Value
Publication number	US-11574575-B2
Application number	US-202117555153-A
Country	US
Kind code	B2
Filing date	Dec 17, 2021
Priority date	Mar 5, 2021
Publication date	Feb 7, 2023
Grant date	Feb 7, 2023

Abstract

Provided are a shift register unit, a shift register, a display panel and a driving method thereof. The shift register unit includes: an input circuit electrically coupled to an input terminal, a first voltage terminal and a pull-up node; an output circuit electrically coupled to the pull-up node, a first clock terminal, a first scan control terminal, a first output terminal and a second output terminal; and a scan control circuit electrically coupled to the second output terminal, a second voltage terminal and a second scan control terminal. The input circuit is configured to write a first voltage provided by the first voltage terminal into the pull-up node in response to a start signal inputted to the input terminal. The output circuit is configured to output a first clock signal from the first clock terminal via the first output terminal, when the pull-up node is at the first voltage.

First claim

What is claimed is:

1. A shift register unit, comprising:
an input circuit, electrically coupled to an input terminal, a first voltage terminal and a pull-up node;
an output circuit, electrically coupled to the pull-up node, a first clock terminal, a first scan control terminal, a first output terminal and a second output terminal; and
a scan control circuit, electrically coupled to the second output terminal, a second voltage terminal and a second scan control terminal,
wherein the input circuit is configured to: write a first voltage provided by the first voltage terminal into the pull-up node in response to a start signal inputted to the input terminal,
the output circuit is configured to: output a first clock signal received by the first clock terminal via the first output terminal, when the pull-up node is at the first voltage; and output the first clock signal via the second output terminal to a gate line, wherein the outputted first clock signal is acted as a gate scan signal, when a first control signal is inputted into the first scan control terminal and a second control signal is inputted into the second scan control terminal,
the scan control circuit is configured to: enable the second voltage terminal and the second output terminal to be electrically coupled, when a third control signal is inputted into the second scan control terminal; and enable the second output terminal and the first output terminal to be electrically disconnected, when a fourth control signal is inputted into the first scan control terminal.

2. The shift register unit according to claim 1 , further comprising:
a pull-down control circuit, electrically coupled to the second clock terminal and the pull-down node, and configured to: write an effective level of a second clock signal into the pull-down node in response to that the second clock terminal receives the second clock signal; and
a pull-down circuit, electrically coupled to the pull-up node, the pull-down node, the second output terminal and the second voltage terminal, and configured to: enable the pull-up node and the second voltage terminal to be electrically connected and enable the second output terminal and the second voltage terminal to be electrically connected, when the pull-down node is at the effective level of the second clock signal.

3. The shift register unit according to claim 2 , further comprising:
a first reset circuit, electrically coupled to a first reset terminal, the pull-up node and the second voltage terminal, and configured to: enable the pull-up node and the second voltage terminal to be electrically connected, in response to a first reset signal inputted by the first reset terminal; and
a second reset circuit, electrically coupled to the pull-up node, a third voltage terminal and a second reset terminal, and configured to: enable the pull-up node and the third voltage terminal to be electrically connected, in response to a second reset signal inputted by the second reset terminal.

4. The shift register unit according to claim 1 , wherein the input circuit comprises a first transistor, a gate electrode of the first transistor is electrically coupled to the input terminal, a first electrode of the first transistor is electrically coupled to the first voltage terminal, and a second electrode of the first transistor is electrically coupled to the pull-up node.

5. The shift register unit according to claim 1 , wherein the output circuit comprises a third transistor, a ninth transistor and a first capacitor;
a gate electrode of the third transistor is electrically coupled to the pull-up node, a first electrode of the third transistor is electrically coupled to the first clock terminal, and a second electrode of the third transistor is electrically coupled to the first output terminal;
a gate electrode of the ninth transistor is electrically coupled to the first scan control terminal, a first electrode of the ninth transistor is electrically coupled to the first output terminal, and a second electrode of the ninth transistor is electrically coupled to the second output terminal; and
two ends of the first capacitor are electrically coupled to the pull-up node and the first output terminal, respectively.

6. The shift register unit according to claim 1 , wherein the scan control circuit comprises a tenth transistor, a gate electrode of the tenth transistor is electrically coupled to the second scan control terminal, a first electrode of the tenth transistor is electrically coupled to the second output terminal, and a second electrode of the tenth transistor is electrically coupled to the second voltage terminal.

7. The shift register unit according to claim 1 , wherein the pull-down control circuit comprises a sixth transistor, a seventh transistor and a second capacitor; a gate electrode of the sixth transistor is electrically coupled to the pull-up node, a first electrode of the sixth transistor is electrically coupled to the pull-down node, and a second electrode of the sixth transistor is electrically coupled to the second voltage terminal; a gate electrode and a first electrode of the seventh transistor are both electrically coupled to the second clock terminal, and a second electrode of the seventh transistor is electrically coupled to the pull-down node; and two ends of the second capacitor are electrically coupled to the pull-down node and the second voltage terminal, respectively, and
wherein the pull-down circuit comprises a fourth transistor and a fifth transistor; a gate electrode of the fourth transistor is electrically coupled to the pull-down node, a first electrode of the fourth transistor is electrically coupled to the second output terminal, a second electrode of the fourth transistor is electrically coupled to the second voltage terminal; and a gate electrode of the fifth transistor is electrically coupled to the pull-down node, a first electrode of the fifth transistor is electrically coupled to the pull-up node, and a second electrode of the fifth transistor is electrically coupled to the second voltage terminal.

8. The shift register unit according to claim 1 , wherein:
the first reset circuit comprises an eighth transistor, a gate electrode of the eighth transistor is electrically coupled to the first reset terminal, a first electrode of the eighth transistor is electrically coupled to the pull-up node, and a second electrode of the eighth transistor is electrically coupled to the second voltage terminal; and
the second reset circuit comprises a second transistor, a gate electrode of the second transistor is electrically coupled to the second reset terminal, a first electrode of the second transistor is electrically coupled to the pull-up node, and a second electrode of the second transistor is electrically coupled to a third voltage terminal.

9. The shift register unit according to claim 1 , further comprising: a pull-down control circuit, a pull-down circuit, a first reset circuit and a second reset circuit, wherein:
the input circuit comprises a first transistor, a gate electrode of the first transistor is electrically coupled to the input terminal, a first electrode of the first transistor is electrically coupled to the first voltage terminal, and a second electrode of the first transistor is electrically coupled to the pull-up node;
the output circuit comprises a third transistor, a ninth transistor and a first capacitor; a gate electrode of the third transistor is electrically coupled to the pull-up node, a first electrode of the third transistor is electrically coupled to the first clock terminal, and a second electrode of the third transistor is electrically coupled to the first output terminal; a gate electrode of the ninth transistor is elect

Assignees

• Beijing Boe Optoelectronics Tech Co Ltd
• Boe Technology Group Co Ltd

Inventors

• Zong Shaolei
• Sun Jigang
• Liu Rui
• Sun Wei
• Duan Xin
• Zhang Junwei

Classifications

• G09G2310/0267

  Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays · CPC title

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title

• G09G2310/0213

  controlling the sequence of the scanning lines with respect to the patterns to be displayed, e.g. to save power · CPC title

• G11C19/28 Primary

  using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title

• G09G3/20 Primary

  for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} · CPC title