Multi-core cable assembling method and multi-core cable assembly producing method

US11570906B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11570906-B2
Application numberUS-202117209770-A
CountryUS
Kind codeB2
Filing dateMar 23, 2021
Priority dateMar 27, 2020
Publication dateJan 31, 2023
Grant dateJan 31, 2023

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

An assembling method for a multi-core cable having a plurality of electrical insulated wires is designed to connect one-end-portions of the electrical insulated wires to electrode patterns, respectively, of one circuit board, correspondingly connect other-end-portions of the electrical insulated wires to electrode patterns, respectively, of the other circuit board, compute intersection coefficients on one end side and the other of the cable, and iterate interchanging connecting destinations for the one-end-portions of the electrical insulated wires, correspondingly interchanging connecting destinations for the other-end-portions of the electrical insulated wires, and computing the intersection coefficients on the one end side and the other of the cable. The connecting destinations for the electrical insulated wires to the electrode patterns are determined in such a manner that a maximum intersection coefficient denoting either larger one of the respective intersection coefficients of the one end side and the other of the cable is made small.

First claim

Opening claim text (preview).

What is claimed is: 1. A method for assembling a multi-core cable configured to include a plurality of electrical insulated wires, and a sheath being provided over the plurality of electrical insulated wires together, to connect the plurality of electrical insulated wires to corresponding respective pluralities of electrode patterns of circuit boards on both end portions of the multi-core cable, the method comprising: arranging the plurality of electrical insulated wires in alignment with each other on both the end portions of the multi-core cable on a flat surface; connecting respective one end portions of the plurality of electrical insulated wires to the respective plurality of electrode patterns of one of the circuit boards, then correspondingly connecting respective other end portions of the plurality of electrical insulated wires to the respective plurality of electrode patterns of an other of the circuit boards, then calculating with a computer coefficients of intersection for the plurality of electrical insulated wires on one end side and an other end side, respectively, of the multi-core cable; and iterating interchanging connecting destinations for the respective one end portions of the plurality of electrical insulated wires to the respective plurality of electrode patterns of the one of the circuit boards, then correspondingly interchanging connecting destinations for the respective other end portions of the plurality of electrical insulated wires to the respective plurality of electrode patterns of the other of the circuit boards, then calculating with the computer the coefficients of intersection for the plurality of electrical insulated wires on the one end side and the other end side, respectively, of the multi-core cable, wherein the connecting destinations for the plurality of electrical insulated wires to the respective pluralities of electrode patterns of the circuit boards are determined with the computer in such a manner that a maximum coefficient of intersection, which refers to either larger one of the respective coefficients of intersection of the one end side and the other end side of the multi-core cable, is made small. 2. The method for assembling the multi-core cable according to claim 1 , wherein, when a laying out order for the plurality of electrical insulated wires in a state of being arranged in alignment with each other on the flat surface is expressed in terms of electric wire numbers N, while a laying out order for the respective plurality of electrode patterns of each of the circuit boards is expressed in terms of electrode numbers E, the respective coefficients of intersection of the one end side and the other end side of the multi-core cable are obtained by adding |E−N| together for all of the plurality of electrical insulated wires, then the connecting destinations for the plurality of electrical insulated wires to the respective pluralities of electrode patterns of the circuit boards are determined with the computer in such a manner that the maximum coefficient of intersection, which refers to either larger one of the respective coefficients of intersection of the one end side and the other end side of the multi-core cable, is made small. 3. The method for assembling the multi-core cable according to claim 2 , including sequentially iterating the steps of obtaining with the computer the maximum coefficient of intersection in an initial state in which the coefficient of intersection on the one end side of the multi-core cable is a minimum, thereafter on the one end side of the multi-core cable, transposing the connecting destinations for an i-th one of the plurality of electrical insulated wires, whose electric wire number N is i-th, and a j-th one of the plurality of electrical insulated wires, whose electric wire number N is j-th represented by the following equations: j=i+h (when i+h≤n ) j=i+h−n (when i+h>n ), where h is a variable, and n is the number of electrical insulated wires, obtaining with the computer the maximum coefficient of intersection in a state of the transposition of the connecting destinations, and when the obtained maximum coefficient of intersection is small as compared with before the transposition of the connecting destinations, making a decision to transpose the connecting destinations, wherein the connecting destinations for the plurality of electrical insulated wires to the respective pluralities of electrode patterns, respectively, of the circuit boards are determined with the computer by iterating the above mentioned steps while incrementing the variable h sequentially from 1. 4. The method for assembling the multi-core cable according to claim 3 , wherein, when a rate of change of the maximum coefficient of intersection before and after the above mentioned steps becomes equal to or smaller than a preset threshold value for the rate of change, the connecting destinations for the plurality of electrical insulated wires at the point of time on both the end portions of the multi-core cable are determined to be the respective pluralities of electrode patterns for the final connecting destinations for the plurality of electrical insulated wires. 5. A method for producing a multi-core cable assembly, which is designed to include a multi-core cable being configured in such a manner as to include a plurality of electrical insulated wires, and a sheath being provided over the plurality of electrical insulated wires together, and circuit boards to be provided on both end portions, respectively, of the multi-core cable, each of the circuit boards having each plurality of electrode patterns thereon to connect with the plurality of electrical insulated wires, respectively, the method comprising: arranging the plurality of electrical insulated wires in alignment with each other on both the end portions of the multi-core cable on a flat surface; connecting respective one end portions of the plurality of electrical insulated wires to the respective plurality of electrode patterns of one of the circuit boards, then correspondingly connecting respective other end portions of the plurality of electrical insulated wires to the respective plurality of electrode patterns of an other of the circuit boards, then calculating with a computer coefficients of intersection for the plurality of electrical insulated wires on one end side and an other end side, respectively, of the multi-core cable; and iterating interchanging connecting destinations for the respective one end portions of the plurality of electrical insulated wires to the respective plurality of electrode patterns, respectively, of the one of the circuit boards, then correspondingly interchanging connecting destinations for the respective other end portions of the plurality of electrical insulated wires to the respective plurality of electrode patterns of the other of the circuit boards, then calculating with the computer the coefficients of intersection for the plurality of electrical insulated wires on the one end side and the other end side, respectively, of the multi-core cable, wherein the connecting destinations for the plurality of electrical insulated wires to the respective pluralities of electrode patterns of the circuit boards are determined with the computer in such a manner that a maximum coefficient of intersection, which refers to either larger one of the respective coefficients of intersection of the one end side and the other end side of the multi-core cable, is made small.

Assignees

Inventors

Classifications

  • Protection against damage caused by external factors, e.g. sheaths or armouring · CPC title

  • for manufacturing co-axial cables (applying discontinuous insulation H01B13/20) · CPC title

  • of the central conductor · CPC title

  • Details relating to the conductive cores · CPC title

  • H05K3/3447Primary

    Lead-in-hole components · CPC title

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Frequently asked questions

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What does patent US11570906B2 cover?
An assembling method for a multi-core cable having a plurality of electrical insulated wires is designed to connect one-end-portions of the electrical insulated wires to electrode patterns, respectively, of one circuit board, correspondingly connect other-end-portions of the electrical insulated wires to electrode patterns, respectively, of the other circuit board, compute intersection coeffici…
Who is the assignee on this patent?
Hitachi Metals Ltd
What technology area does this patent fall under?
Primary CPC classification H05K3/3447. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jan 31 2023 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).