Methods to mitigate denial of service attacks on time synchronization using link redundancy for industrial/autonomous systems

Patent metadata

Field	Value
Publication number	US-11570732-B2
Application number	US-202017032921-A
Country	US
Kind code	B2
Filing date	Sep 25, 2020
Priority date	Sep 25, 2020
Publication date	Jan 31, 2023
Grant date	Jan 31, 2023

Abstract

Systems and methods in which devices synchronize their clocks for purposes of data transmission are described. Particularly, the disclosed systems and methods provide detection and mitigation of interference by malicious (or non-malicious) wireless devices with communication of time synchronized data over wireless networks. Systems and methods are provided where times statistics related to multiple instances of wireless time synchronization are collected and collated. Devices in the system can discipline their internal clocks based on the collated time statistics.

First claim

What is claimed is:

1. A computing apparatus comprising:
circuitry at a follower device; and
a memory device at the follower device, the memory storing instructions that, when executed by the circuitry, configure the apparatus to:
collect time statistics for a first instance of wireless time synchronization between the follower device and a leader device, the first instance of wireless time synchronization on a first channel of a wireless network;
collect time statistics for a second instance of wireless time synchronization between the follower device and the leader device, the second instance of wireless time synchronization on a second channel of the wireless network different from the first channel of the wireless network;
collate the time statistics for the first instance of wireless time synchronization and the second instance of wireless time synchronization;
detect a security attack based on the time statistics; and
discipline an internal clock of the follower device based on the collated time statistics.

2. The computing apparatus of claim 1 , the memory device storing instructions that, when executed by the circuitry, configure the apparatus to:
establish the first instances of wireless time synchronization; and
establish the second instance of wireless time synchronization.

3. The computing apparatus of claim 1 , the memory device storing instructions that, when executed by the circuitry, configure the apparatus to:
send a first request to the leader device comprising indications to establish the first instance of wireless time synchronization; and
send a second request to the leader device comprising indications to establish the second instance of wireless time synchronization.

4. The computing apparatus of claim 3 , wherein the first request comprises an indication to establish the first instance of wireless time synchronization on the first channel of the wireless network and wherein the second request comprises an indication to establish the second instance of wireless time synchronization on the second channel of the wireless network different from the first channel of the wireless network.

5. The computing apparatus of claim 3 , wherein the first instance of wireless time synchronization and the second instance of wireless time synchronization are established based on the Institute of Electrical and Electronics Engineers (IEEE) 802.1AS or 802.1Qbv standards.

6. The computing apparatus of claim 1 , the memory device storing instructions that, when executed by the circuitry, configure the apparatus to:
receive a first message from the leader device, the first message comprising an indication of a first time stamp;
send a first message acknowledgement to the leader device, the first message acknowledgement comprising an indication of a second time stamp;
receive a second message from the leader device, the second message comprising an indication of a third time stamp and a first time differential; and
send a second message acknowledgement to the leader device, the second message acknowledgement comprising an indication of a fourth time stamp,
wherein the time statistics for the first instance of wireless time synchronization between the follower device and the leader device are based on the first time stamp, the second time stamp, the third times stamp, the fourth time stamp, and the first time differential.

7. The computing apparatus of claim 6 , wherein the first time differential comprises a difference between the first time stamp and a time at which the leader device received the first message acknowledgement.

8. The computing apparatus of claim 6 , the memory device storing instructions that, when executed by the circuitry, configure the apparatus to derive, by the circuitry at the follower device, a mean drift of the first time stamp, the second time stamp, the third times stamp, the fourth time stamp, and the first time differential.

9. The computing apparatus of claim 8 , the memory device storing instructions that, when executed by the circuitry, configure the apparatus to discipline the internal clock based on a lower of the mean drift of the first instance of wireless time synchronization or the mean drift of the second instance of wireless time synchronization.

10. A method, comprising:
collecting, by circuitry at a follower device, time statistics for a first instance of wireless time synchronization between the follower device and a leader device, the first instance of wireless time synchronization on a first channel of a wireless network;
collecting, by the circuitry at the follower device, time statistics for a second instance of wireless time synchronization between the follower device and the leader device, the second instance of wireless time synchronization on a second channel of the wireless network different from the first channel of the wireless network;
collating, by the circuitry at the follower device, the time statistics for the first instance of wireless time synchronization and the second instance of wireless time synchronization;
detect, by the circuitry at the follower device, a security attack based on the time statistics; and
disciplining, by the circuitry at the follower device, an internal clock of the follower device based on the collated time statistics.

11. The method of claim 10 , comprising:
establishing, between the follower device and the leader device, the first instances of wireless time synchronization; and
establishing, between the follower device and the leader device, the second instance of wireless time synchronization.

12. The method of claim 11 , comprising:
sending, by the circuitry at the follower device, a first request to the leader device comprising indications to establish the first instance of wireless time synchronization; and
sending, by the circuitry at the follower device, a request to the leader device comprising indications to establish the first instance of wireless time synchronization on a first channel, different than the first channel, of a wireless network.

13. The method of claim 12 , wherein the first request comprises an indication to establish the first instance of wireless time synchronization on the first channel of the wireless network and wherein the second request comprises an indication to establish the second instance of wireless time synchronization on the second channel of the wireless network different from the first channel of the wireless network.

14. The method of claim 12 , wherein the first instance of wireless time synchronization and the second instance of wireless time synchronization are established based on the Institute of Electrical and Electronics Engineers (IEEE) 802.1AS or 802.1Qbv standards.

15. The method of claim 10 , collecting, by the circuitry at the follower device, time statistics for the first instance of wireless time synchronization between the follower device and the leader device comprising:
receiving, by the circuitry at the follower device, a first message from the leader device, the first message comprising an indication of a first time stamp;
sending, by the circuitry at the follower device, a first message acknowledgement to the leader device, the first message acknowledgement comprising an indication of a second time stamp;
receiving, by the circuitry at the follower device, a second message from the leader device, the second message comprising an indication of a third time stamp and a first time differential; and
sending, by the circuitry at the follower device, a second message acknowledgement to the leader device, the second message acknowledgement co

Assignees

• Intel Corp

Inventors

• Perez-Ramirez Javier
• Galeev Mikhail
• Sudhakaran Susruth
• Cavalcanti Dave
• Sastry Manoj R
• Gutierrez Christopher N

Classifications

• H04L63/1458

  Denial of Service · CPC title

• H04W56/001 Primary

  Synchronization between nodes · CPC title

• G06F1/12

  Synchronisation of different clock signals {provided by a plurality of clock generators} · CPC title

• H04W12/122

  Counter-measures against attacks; Protection against rogue devices · CPC title

• H04K2203/16

  for telephony · CPC title