Systems and methods for asymmetric image splitter clock generation

Patent metadata

Field	Value
Publication number	US-11570400-B2
Application number	US-201916381267-A
Country	US
Kind code	B2
Filing date	Apr 11, 2019
Priority date	Jun 13, 2018
Publication date	Jan 31, 2023
Grant date	Jan 31, 2023

Abstract

Described herein are systems and methods that provide for asymmetric image splitter image stream applications. In one embodiment, a system supporting image multi-streaming comprises an asymmetric image splitter engine that splits super-frame image streams into two or more image streams and a fractional clock divider circuit. The fractional clock divider may comprise a digital feedback control loop and a one-bit sigma delta modulator. The fractional clock divider circuit may provide compatible display clock frequencies for each of the two or more image streams. When a multi-image stream comprises the two image streams, the asymmetric image splitter engine adjusts a vertical asymmetry of a first image stream with a shortest height to same height as a second image stream by adding vertical padding to the first image stream. The super-frame image streams may comprise image streams from video, LIDAR, radar, or other sensors.

First claim

What is claimed is:

1. A system supporting image multi-streaming comprising:
an asymmetric image splitter engine that splits super-frame image streams into two or more image streams; and
a fractional clock divider circuit comprising a digital feedback control loop,
wherein the fractional clock divider circuit provides compatible display clock frequencies for each of the two or more image streams without an incorporation of one or more phase-lock-loop (PLL) oscillators.

2. The system of claim 1 , wherein when a multi-streaming image comprises the two or more image streams, the asymmetric image splitter engine adjusts a vertical asymmetry of a first image stream with a shortest height to same height as a second image stream by adding vertical padding to the first image stream.

3. The system of claim 1 , wherein the system utilizes a serializer and a deserializer (SerDes).

4. The system of claim 1 , wherein the fractional clock divider circuit further comprises a one-bit sigma delta modulator.

5. The system of claim 4 , wherein the one-bit sigma delta modulator comprises a digital adder/subtractor and a comparator block.

6. The system of claim 1 , wherein the digital feedback control loop comprises a first-in-first out (FIFO) counter and a programmable threshold.

7. The system of claim 6 , wherein a difference between a value of the FIFO counter and a value of the programmable threshold is an error signal, wherein when the error signal is multiplied by a programmable feedback gain, a proportional feedback is generated to adjust a number of pixels in a split display's frame.

8. The system of claim 1 , wherein the super-frame image streams comprise video images.

9. The system of claim 1 , wherein the super-frame image streams comprise image streams supporting Advanced Driver-Assistance Systems (ADAS) or automotive infotainment applications.

10. The system of claim 1 , wherein the super-frame image streams comprise image streams from Light Detection and Ranging (LIDAR) devices, radar, or other sensors.

11. A method comprising:
receiving a multi-image stream comprising super frame image streams, wherein each super-frame image stream includes a first image stream and a second image stream and wherein a height of the first image stream is higher than the second image stream;
adjusting a vertical asymmetry of the second image stream to same height as the first image stream by adding vertical padding to the second image stream;
utilizing an asymmetric image splitter engine to split the super-frame image streams into two separate image streams;
generating compatible display clock frequencies for each of the two separate image streams without an incorporation of one or more phase-lock-loop (PLL) oscillators; and
utilizing a fractional clock divider circuit to generate the compatible display clock frequencies.

12. The method of claim 11 , wherein the fractional clock divider circuit comprises a digital feedback control loop and a one-bit sigma delta modulator.

13. The method of claim 12 , wherein the one-bit sigma delta modulator comprises a digital adder/subtractor and a comparator block, wherein individual display clocks are generated based on an output of the comparator block.

14. The method of claim 12 , wherein the digital feedback control loop comprises an up-down first-in-first-out (FIFO) counter, a programmable threshold and a programmable feedback gain that collectively provide a proportional feedback to adjust a number of pixels in a split display's frame.

15. The method of claim 11 , wherein the super-frame image streams comprise video images.

16. A non-transitory computer readable storage medium having computer program code stored thereon, the computer program code, when executed by one or more processors implemented on a communication device, causes the communication device to perform a method comprising:
receiving a multi-image stream comprising super frame image streams, wherein each super-frame image stream includes a first image stream and a second image stream and wherein a height of the first image stream is higher than the second image stream;
adjusting a vertical asymmetry of the second image stream to same height as the first image stream by adding vertical padding to the second image stream;
utilizing an asymmetric image splitter engine to split the super-frame image streams into two separate image streams; and
utilizing a fractional clock divider circuit to generate compatible display clock frequencies for each of the two separate image streams without an incorporation of one or more phase-lock-loop (PLL) oscillators.

17. The non-transitory computer readable storage medium of claim 16 , wherein the super-frame image streams comprise image streams from video, Light Detection and Ranging (LIDAR) devices, radar, or other sensors.

18. The non-transitory computer readable storage medium of claim 16 , wherein the fractional clock divider circuit comprises a digital feedback control loop and a one-bit sigma delta modulator.

Assignees

• Maxim Integrated Products
• Analog Devices Inc

Inventors

• Balcioglu Yalcin

Classifications

• H03L7/1974

  for fractional frequency division · CPC title

• H04L7/0331

  with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock (H04L7/0337 takes precedence) · CPC title

• H04N21/234

  Processing of video elementary streams, e.g. splicing of video streams or manipulating encoded video stream scene graphs · CPC title

• H04N7/104

  Switchers or splitters · CPC title

• H04N21/41422 Primary

  located in transportation means, e.g. personal vehicle (arrangements specially adapted for transportation systems in broadcast systems H04H20/62) · CPC title