Transimpedance amplifier

Patent metadata

Field	Value
Publication number	US-11569785-B2
Application number	US-201917289908-A
Country	US
Kind code	B2
Filing date	Oct 18, 2019
Priority date	Nov 2, 2018
Publication date	Jan 31, 2023
Grant date	Jan 31, 2023

Abstract

A negative feedback inductor and a gate inductor are formed in different wiring layers of a substrate so as to be at least partially overlapped with each other in a plan view. When the lower wiring layer is thinner and the upper wiring layer is thicker, the negative feedback inductor Lc is formed in the lower wiring layer that is thinner.

First claim

The invention claimed is:

1. A transimpedance amplifier comprising:
a MOS transistor;
a resistor having a first end connected to a drain of the MOS transistor;
a first inductor having a first end connected to a second end of the resistor, and wherein a second end of the first inductor is directly connected to a current signal input line;
a second inductor having a first end connected to a gate of the MOS transistor, and wherein a second end of the second inductor is directly connected to the current signal input line;
a substrate on which the first inductor and the second inductor are disposed; and
a plurality of wiring layers over the substrate, wherein the first inductor and the second inductor are disposed in different wiring layers of the plurality of wiring layers so as to be at least partially overlapped with each other in a plan view.

2. The transimpedance amplifier according to claim 1 , wherein the first inductor is disposed in a first wiring layer of the plurality of wiring layers, wherein the second inductor is disposed in a second wiring layer of the plurality of wiring layers, and wherein the first wiring layer that is thinner than the second wiring layer.

3. The transimpedance amplifier according to claim 1 , wherein the first inductor and the second inductor are arranged so as to generate magnetic fields that reinforce each other.

4. The transimpedance amplifier according to claim 1 , wherein the first inductor is a first multilayer inductor that includes a plurality of first inductors in layers of the plurality of wiring layers and connected to each other.

5. The transimpedance amplifier according to claim 4 , wherein the second inductor is a second multilayer inductor that includes a plurality of second inductors in layers of the plurality of wiring layers and connected to each other.

6. A transimpedance amplifier comprising:
a first MOS transistor having a first source that is grounded;
a second MOS transistor having a second source connected to a power supply;
a resistor having a first end connected to a connection point between a first drain of the first MOS transistor and a second drain of the second MOS transistor;
a first inductor connected between a second end of the resistor and a current signal input line;
a second inductor connected between a first gate of the first MOS transistor and the current signal input line;
a third inductor connected between a second gate of the second MOS transistor and the current signal input line;
a substrate on which the first inductor, the second inductor, and the third inductor are disposed; and
a plurality of wiring layers over the substrate, wherein the first inductor, the second inductor, and the third inductor are disposed in different wiring layers of the plurality of wiring layers such that the first inductor is at least partially overlapped with the second inductor and the third inductor in a plan view.

7. The transimpedance amplifier according to claim 6 , wherein the first inductor is disposed in a first wiring layer that is thinner than a second wiring layer in which the second inductor or the third inductor are disposed.

8. The transimpedance amplifier according to claim 7 , wherein the second inductor and the third inductor are both disposed in the second wiring layer.

9. The transimpedance amplifier according to claim 6 , wherein the first inductor, the second inductor, and the third inductor are each a multilayer inductor that includes a plurality of inductors that are disposed in layers of the plurality of wiring layers and are connected to each other.

10. A method comprising:
forming a MOS transistor at a top surface of a substrate; and
forming a plurality of wiring layers over the substrate, the plurality of wiring layers comprising:
a resistor having a first end connected to a drain of the MOS transistor;
a first inductor having a first end connected to a second end of the resistor, and wherein a second end of the first inductor is directly connected to a current signal input line; and
a second inductor having a first end connected to a gate of the MOS transistor, and wherein a second end of the second inductor is directly connected to the current signal input line, wherein the first inductor and the second inductor are disposed in different wiring layers of the plurality of wiring layers, and wherein the first inductor at least partially overlaps the second inductor in in a plan view.

11. The method according to claim 10 , wherein the first inductor is disposed in a first wiring layer of the plurality of wiring layers, wherein the second inductor is disposed in a second wiring layer of the plurality of wiring layers, and wherein the first wiring layer that is thinner than the second wiring layer.

12. The method according to claim 10 , wherein the first inductor and the second inductor are arranged so as to generate magnetic fields that reinforce each other.

13. The method according to claim 10 , wherein the first inductor is a first multilayer inductor that includes a plurality of first inductors in layers of the plurality of wiring layers and connected to each other.

14. The method according to claim 13 , wherein the second inductor is a second multilayer inductor that includes a plurality of second inductors in layers of the plurality of wiring layers and connected to each other.

Assignees

• Nippon Telegraph & Telephone

Inventors

• Tanaka Kenji
• Miura Naoki
• Fukuyama Hiroyuki
• Nosaka Hideyuki

Classifications

• H01F41/061

  Winding flat conductive wires or sheets · CPC title

• H03F1/34 Primary

  Negative-feedback-circuit arrangements with or without positive feedback (H03F1/02 - H03F1/30, H03F1/38 - H03F1/50, H03F3/50 take precedence {; for rejection of common mode signals H03F3/45479}) · CPC title

• H01F27/2866

  Combination of wires and sheets · CPC title

• H03F1/48

  of aperiodic amplifiers · CPC title

• H03F3/70

  Charge amplifiers · CPC title