Semiconductor device

Patent metadata

Field	Value
Publication number	US-11569351-B2
Application number	US-202117242460-A
Country	US
Kind code	B2
Filing date	Apr 28, 2021
Priority date	Jun 9, 2020
Publication date	Jan 31, 2023
Grant date	Jan 31, 2023

Abstract

A main semiconductor device element has first and second p + -type high-concentration regions that mitigate electric field applied to bottoms of trenches. The first p + -type high-concentration regions are provided separate from p-type base regions, face the bottoms of the trenches in a depth direction, and extend in a linear shape in a first direction that is a same direction in which the trenches extend. Between adjacent trenches of the trenches, the second p + -type high-concentration regions are provided scattered in the first direction, separate from the first p + -type high-concentration regions and the trenches and in contact with the p-type base regions. Between the second p + -type high-concentration regions adjacent to one another in the first direction, n-type current spreading regions or n + -type high-concentration regions having an impurity concentration higher than that of the n-type current spreading regions are provided in contact with the second p + -type high-concentration regions.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a semiconductor substrate containing a semiconductor having a bandgap wider than that of silicon, the semiconductor substrate having a first main surface and a second main surface opposite to each other;
a first semiconductor region of a first conductivity type, provided in the semiconductor substrate;
a second semiconductor region of a second conductivity type, provided between the first main surface of the semiconductor substrate and the first semiconductor region;
a plurality of third semiconductor regions of the first conductivity type, each selectively provided between the first main surface of the semiconductor substrate and the second semiconductor region;
a plurality of trenches each penetrating through the third semiconductor regions and the second semiconductor region, and reaching the first semiconductor region;
a plurality of first high-concentration regions of the second conductivity type, each of which is selectively provided in the first semiconductor region and faces a respective one of bottoms of the trenches in a depth direction, the first high-concentration regions having an impurity concentration higher than an impurity concentration of the second semiconductor region;
a plurality of second high-concentration regions of the second conductivity type, each of which is selectively provided in the first semiconductor region, is separate from the first high-concentration regions and the trenches, and is in contact with the second semiconductor region, the second high-concentration regions reaching positions deeper from the second semiconductor region than are the bottoms of the trenches and having an impurity concentration higher than the impurity concentration of the second semiconductor region;
a plurality of gate electrodes each provided in a respective one of the trenches via a respective one of a plurality of gate insulating films;
a first electrode electrically connected to the second semiconductor region, the third semiconductor regions, the first high-concentration regions, and the second high-concentration regions; and
a second electrode provided on the second main surface of the semiconductor substrate, wherein
the trenches each have a linear shape that extends in a first direction parallel to the first main surface of the semiconductor substrate,
the first high-concentration regions each have a linear shape that extends in the first direction, and
the second high-concentration regions are apart from one another by a predetermined interval in the first direction,
the semiconductor device further comprising a plurality of fourth semiconductor regions of the first conductivity type, each of which extends from a respective one of the first high-concentration regions to a respective one of the second high-concentration regions that are adjacent to each other in a second direction parallel to the semiconductor substrate and orthogonal to the first direction, and also extends from the respective one of the second high-concentration regions to a respective another one of the second high-concentration regions that are adjacent to each other in the first direction, the fourth semiconductor regions having an impurity concentration higher than an impurity concentration of the first semiconductor region.

2. The semiconductor device according to claim 1 , further comprising
a plurality of third high-concentration regions of the first conductivity type, selectively provided in the first semiconductor region, each of which is separate from the first high-concentration regions and the trenches, and is in contact with the second semiconductor region, the third high-concentration regions reaching positions deeper than are the bottoms of the trenches as measured from the second semiconductor region and having an impurity
concentration higher than an impurity concentration of the first semiconductor region, wherein the third high-concentration regions are each provided between a respective pair of the second high-concentration regions that are adjacent to each other in the first direction, each of the third high-concentration regions being adjacent to the respective pair of the second high-concentration regions in the first direction.

3. The semiconductor device according to claim 2 , wherein
the second high-concentration regions and the third high-concentration regions are disposed to repeatedly alternate with one another in the first direction.

4. The semiconductor device according to claim 2 , wherein
an impurity concentration of the first conductivity type of the third high-concentration regions is a same as an impurity concentration of the second conductivity type of the second high-concentration regions.

5. The semiconductor device according to claim 2 , wherein
a width of each of the second high-concentration regions in the first direction is narrower than a width of the each of the second high-concentration regions in the second direction.

6. The semiconductor device according to claim 2 , wherein
a width of each of the third high-concentration regions in the first direction is a same measurement as a width of each of the second high-concentration regions in the first direction.

7. The semiconductor device according to claim 2 , wherein
a width of each of the third high-concentration regions in the second direction is a same measurement as a width of each of the second high-concentration regions in the second direction.

8. The semiconductor device according to claim 2 , further comprising
a plurality of fourth semiconductor regions of the first conductivity type, each of which extends from a respective one of the first high-concentration regions to a respective one of the second high-concentration regions that are adjacent to each other in the second direction, and also extends from the respective one of the first high-concentration regions to a respective one of the third high-concentration regions that are adjacent to each other in the second direction, the fourth semiconductor regions having an impurity concentration higher than an impurity concentration of the first semiconductor region, wherein
the impurity concentration of the third high-concentration regions is higher than the impurity concentration of the fourth semiconductor regions.

9. A semiconductor device, comprising:
a semiconductor substrate containing a semiconductor having a bandgap wider than that of silicon, the semiconductor substrate having a first main surface and a second main surface opposite to each other;
a first semiconductor region of a first conductivity type, provided in the semiconductor substrate;
a second semiconductor region of a second conductivity type, provided between the first main surface of the semiconductor substrate and the first semiconductor region;
a plurality of third semiconductor regions of the first conductivity type, each selectively provided between the first main surface of the semiconductor substrate and the second semiconductor region;
a plurality of trenches each penetrating through the third semiconductor regions and the second semiconductor region, and reaching the first semiconductor region;
a plurality of first high-concentration regions of the second conductivity type, each of which is selectively provided in the first semiconductor region and faces a respective one of bottoms of the trenches in a depth direction, the first high-concentration regions having an impurity concentration higher than an impurity concentration of the second semiconductor region;
a plurality of second high-concentration regions of the second conductivity type, each of which is selectively provided in the first semiconductor region, is separate from

Assignees

• Fuji Electric Co Ltd

Inventors

• Hoshi Yasuyuki

Classifications

• H01L29/4236

  Electricity · mapped topic

• H01L29/7813

  Electricity · mapped topic

• H01L29/0696

  Electricity · mapped topic

• H01L29/0856 Primary

  Electricity · mapped topic

• H10D64/513

  within recesses in the substrate, e.g. trench gates, groove gates or buried gates · CPC title