Memory device with transistors above memory stacks and manufacturing method of the memory device

Patent metadata

Field	Value
Publication number	US-11569256-B2
Application number	US-202016817187-A
Country	US
Kind code	B2
Filing date	Mar 12, 2020
Priority date	Sep 19, 2019
Publication date	Jan 31, 2023
Grant date	Jan 31, 2023

Abstract

A device includes a stack above a substrate in a first direction perpendicular to a surface of the substrate, the stack including conductive layers; a semiconductor layer neighboring the stack in a second direction parallel to the surface of the substrate; a memory layer between the first stack and the semiconductor layer; memory cells between the conductive layers and the semiconductor layer; a first transistor connected between one end of the semiconductor layer in a third direction parallel to the surface of the substrate and crossing the second direction and a first interconnect in the first direction; and a second transistor connected between the other end of the semiconductor layer and a second interconnect in the first direction.

First claim

What is claimed is:

1. A memory device comprising:
a substrate;
a first stack provided above the substrate in a first direction perpendicular to a surface of the substrate, the first stack including a first conductive layer, and a second conductive layer provided between the substrate and the first conductive layer;
a first semiconductor layer extending in the first direction and neighboring the first stack in a second direction parallel to the surface of the substrate;
a first memory layer provided between the first stack and the first semiconductor layer;
a first memory cell provided between the first conductive layer and the first semiconductor layer;
a second memory cell provided between the second conductive layer and the first semiconductor layer;
a first transistor provided above the first semiconductor layer in the first direction, the first transistor including a first terminal connected to one end of the first semiconductor layer in a third direction which is parallel to the surface of the substrate and crosses the second direction, and a second terminal connected to a first interconnect;
a second transistor provided above the first semiconductor layer in the first direction, the second transistor including a third terminal connected to the other end of the first semiconductor layer in the third direction, and a fourth terminal connected to a second interconnect;
a second stack provided above the substrate in the first direction and neighboring the first semiconductor layer in the second direction, the second stack including a third conductive layer, and a fourth conductive layer provided between the substrate and the third conductive layer;
a second semiconductor layer provided between the second stack and the first semiconductor layer;
a second memory layer provided between the second semiconductor layer and the second stack;
a third memory cell provided between the third conductive layer and the second semiconductor layer; and
a fourth memory cell provided between the fourth conductive layer and the second semiconductor layer,
wherein
one end of the second semiconductor layer in the third direction is connected to the first terminal of the first transistor, and
the other end of the second semiconductor layer in the third direction is connected to the third terminal of the second transistor.

2. The memory device of claim 1 , wherein the first semiconductor layer includes:
a first portion provided at one end of the first semiconductor layer and connected to the first interconnect via the first transistor;
a second portion provided at the other end of the first semiconductor layer and connected to the second interconnect via the second transistor; and
a third portion provided between the first portion and the second portion.

3. The memory device of claim 2 , wherein an impurity concentration of the first portion and an impurity concentration of the second portion are higher than an impurity concentration of the third portion.

4. The memory device of claim 1 , wherein
the first transistor includes:
a third semiconductor layer extending in the first direction; and
a first gate insulating layer between a fifth conductive layer extending in the third direction and a side surface of the third semiconductor layer, and

the second transistor includes:
a fourth semiconductor layer extending in the first direction; and
a second gate insulating layer between the fifth conductive layer and a side surface of the fourth semiconductor layer.

5. The memory device of claim 1 , wherein the first memory layer includes:
a charge storage layer;
a first insulating layer between the charge storage layer and the first semiconductor layer; and
a second insulating layer between the charge storage layer and the first stack.

6. The memory device of claim 1 , further comprising:
a fifth semiconductor layer provided above the substrate, the fifth semiconductor layer neighboring the first semiconductor layer in the third direction and neighboring the first stack in the second direction;
a third memory layer provided between the fifth semiconductor layer and the first stack;
a fifth memory cell provided between the first conductive layer and the fifth semiconductor layer;
a sixth memory cell provided between the second conductive layer and the fifth semiconductor layer;
a third transistor provided above the fifth semiconductor layer in the first direction, the third transistor including a fifth terminal connected to one end of the fifth semiconductor layer in the third direction, and a sixth terminal connected to a third interconnect; and
a fourth transistor provided above the fifth semiconductor layer in the first direction, the fourth transistor including a seventh terminal connected to the other end of the fifth semiconductor layer in the third direction, and an eighth terminal connected to a fourth interconnect.

7. The memory device of claim 6 , wherein
the first transistor includes:
a sixth semiconductor layer extending in the first direction; and
a third gate insulating layer between a fifth conductive layer extending in the third direction and a side surface of the sixth semiconductor layer,

the second transistor includes:
a seventh semiconductor layer extending in the first direction; and
a fourth gate insulating layer between the fifth conductive layer and a side surface of the seventh semiconductor layer,

the third transistor includes:
an eighth semiconductor layer extending in the first direction; and
a fifth gate insulating layer between the fifth conductive layer and a side surface of the eighth semiconductor layer, and

the fourth transistor includes:
a ninth semiconductor layer extending in the first direction; and
a sixth gate insulating layer between the fourth fifth conductive layer and a side surface of the ninth semiconductor layer.

8. The memory device of claim 6 , further comprising:
a third insulating layer provided between the first semiconductor layer and the third semiconductor layer and between the first memory layer and the third memory layer.

9. The memory device of claim 1 , wherein the first transistor and the second transistor are arranged in a fourth direction, the fourth direction being parallel to the surface of the substrate and crossing the second direction and the third direction.

10. The memory device of claim 1 , further comprising:
a seventh conductive layer extending over one end of the first semiconductor layer and one end of the second semiconductor layer;
an eighth conductive layer extending over the other end of the first semiconductor layer and the other end of the second semiconductor layer;
wherein
the first transistor is provided between the seventh conductive layer and the first interconnect, and
the second transistor is provided between the eighth conductive layer and the second interconnect.

11. The memory device of claim 10 , wherein
the first transistor includes:
a tenth semiconductor layer extending in the first direction and provided on the seventh conductive layer; and
a seventh gate insulating layer between a ninth conductive layer extending in the third direction and a side surface of the tenth semiconductor layer, and

the second transistor includes:
an eleventh semiconductor layer extending in the first direction and provided on the eighth conductive layer; and
an eighth gate insulating layer between the ninth conductive layer and a side surface of the eleventh semiconductor layer.

12. The memory device of claim 1 , wherein
the first conductive layer is provided in a first word line,
the second conductive layer is provided in a second

Assignees

• Kioxia Corp

Inventors

• Naruke Kiyomi
• Shiratake Shinichiro
• Okajima Mutsumi
• Saito Hidetoshi
• Inoue Hirofumi

Classifications

• G11C16/16

  for erasing blocks, e.g. arrays, words, groups · CPC title

• G11C16/08

  Address circuits; Decoders; Word-line control circuits · CPC title

• H01L27/11582 Primary

  Electricity · mapped topic

• H01L23/5283

  Electricity · mapped topic

• H01L27/11565

  Electricity · mapped topic