Methods of forming capacitor structures

Patent metadata

Field	Value
Publication number	US-11569221-B2
Application number	US-202117358251-A
Country	US
Kind code	B2
Filing date	Jun 25, 2021
Priority date	Jun 27, 2019
Publication date	Jan 31, 2023
Grant date	Jan 31, 2023

Abstract

Methods of forming a capacitor structure might include forming a first and second conductive regions having first and second conductivity types, respectively, in a semiconductor material, forming a dielectric overlying the first and second conductive regions, forming a conductor overlying the dielectric, and patterning the conductor, the dielectric, and the first and second conductive regions to form a first island of the first conductive region, a second island of the first conductive region, an island of the second conductive region, a first portion of the dielectric overlying the first island of the first conductive region separated from a second portion of the dielectric overlying the second island of the first conductive region and the island of the second conductive region, and a first portion of the conductor overlying the first portion of the dielectric separated from a second portion of the conductor overlying the second portion of the dielectric.

First claim

What is claimed is:

1. A method of forming a capacitor structure, comprising:
forming a first conductive region having a first conductivity type in a semiconductor material;
forming a second conductive region having a second conductivity type, different than the first conductivity type, in the semiconductor material;
forming a dielectric overlying the first conductive region and overlying the second conductive region;
forming a conductor overlying the dielectric; and
patterning the conductor, the dielectric, the first conductive region and the second conductive region to form a first island of the first conductive region, a second island of the first conductive region, an island of the second conductive region, a first portion of the dielectric overlying the first island of the first conductive region separated from a second portion of the dielectric overlying the second island of the first conductive region and overlying the island of the second conductive region, and a first portion of the conductor overlying the first portion of the dielectric separated from a second portion of the conductor overlying the second portion of the dielectric.

2. The method of claim 1 , wherein forming the first conductive region and forming the second conductive region comprises forming the first conductive region to be separated from the second conductive region by a portion of the semiconductor.

3. The method of claim 1 , wherein forming the first conductive region having the first conductivity type in the semiconductor material comprises forming the first conductive region having the first conductivity type in the semiconductor material having the second conductivity type.

4. The method of claim 3 , wherein forming the first conductive region having the first conductivity type in the semiconductor material having the second conductivity type comprises forming the first conductive region to have an n-type conductivity in the semiconductor material to have a p-type conductivity.

5. The method of claim 4 , wherein forming the second conductive region having the second conductivity type comprises forming the second conductive region to have the p-type conductivity having a higher conductivity level than the semiconductor.

6. The method of claim 1 , further comprising:
removing the second portion of the conductor and the second portion of the dielectric; and
forming a third conductive region extending from the second island of the first conductive region to the island of the second conductive region.

7. The method of claim 6 , wherein forming the third conductive region comprises forming the third conductive region to have a conductivity type selected from a group consisting of the first conductivity type and the second conductivity type.

8. A method of forming a capacitor structure, comprising:
forming a first conductive region having a first conductivity type in a semiconductor material having a second conductivity type, different than the first conductivity type;
forming a second conductive region having the second conductivity type in the semiconductor material, wherein the second conductive region has a higher conductivity level than the semiconductor material;
forming a dielectric overlying the first conductive region and overlying the second conductive region;
forming a conductor overlying the dielectric;
patterning the conductor, the dielectric, the first conductive region and the second conductive region to form a first island of the first conductive region, a second island of the first conductive region, an island of the second conductive region, a first portion of the dielectric overlying the first island of the first conductive region separated from a second portion of the dielectric overlying the second island of the first conductive region and overlying the island of the second conductive region, and a first portion of the conductor overlying the first portion of the dielectric separated from a second portion of the conductor overlying the second portion of the dielectric;
removing the second portion of the conductor and the second portion of the dielectric; and
forming a third conductive region extending from the second island of the first conductive region to the island of the second conductive region.

9. The method of claim 8 , wherein forming the first conductive region having the first conductivity type in the semiconductor material having the second conductivity type comprises forming the first conductive region as a conductively doped monocrystalline silicon region having an n-type conductivity in a monocrystalline silicon semiconductor material having a p-type conductivity.

10. The method of claim 9 , wherein forming the third conductive region comprises forming an n-type conductively doped silicon material.

11. The method of claim 10 , wherein the n-type conductively doped silicon material is selected from a group consisting of an n-type conductively doped monocrystalline silicon and an n-type conductively doped polysilicon.

12. The method of claim 9 , wherein forming the conductor comprises forming a conductively doped polysilicon having a conductivity type selected from a group consisting of the n-type conductivity and the p-type conductivity.

13. The method of claim 8 , wherein forming the dielectric comprises forming a thermal oxide of the first island of the first conductive region, forming a thermal oxide of the second island of the first conductive region, forming a thermal oxide of the island of the second conductive region, and forming a thermal oxide of exposed portions of the semiconductor material.

14. The method of claim 8 , further comprising:
discharging a static charge stored by the first conductive region to the second conductive region after patterning the conductor, the dielectric, the first conductive region and the second conductive region and before grounding the first portion of the conductor.

15. The method of claim 8 , further comprising:
discharging a static charge stored by the first conductive region to the second conductive region after forming the third conductive region and before grounding the first portion of the conductor.

16. A method of forming a capacitor structure, comprising:
forming a first conductive region having a first conductivity type in a semiconductor material having a second conductivity type different than the first conductivity type;
forming a second conductive region having the second conductivity type in the semiconductor material and separated from the first conductive region by a portion of the semiconductor material;
forming a dielectric overlying the first conductive region, overlying the second conductive region, and overlying the portion of the semiconductor material;
forming a conductor overlying the dielectric; and
patterning the conductor, the dielectric, the first conductive region and the second conductive region to form a first island of the first conductive region, a second island of the first conductive region, an island of the second conductive region, a first portion of the dielectric overlying the first island of the first conductive region separated from a second portion of the dielectric overlying the second island of the first conductive region, overlying the portion of the semiconductor material and overlying the island of the second conductive region, and a first portion of the conductor overlying the first portion of the dielectric separated from a second portion of the conductor overlying the second portion of the dielectric.

17. The method of claim 16 , wherein patterning the firs

Assignees

• Micron Technology Inc

Inventors

• Mikhalev Vladimir
• Violette Michael

Classifications

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• H01L29/456

  Electricity · mapped topic

• H01L23/62

  Electricity · mapped topic

• H01L27/0248 Primary

  Electricity · mapped topic

• H01L27/11551

  Electricity · mapped topic