Substrate bonding pad having a multi-surface trace interface

US11569155B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11569155-B2
Application numberUS-202117343069-A
CountryUS
Kind codeB2
Filing dateJun 9, 2021
Priority dateJun 9, 2021
Publication dateJan 31, 2023
Grant dateJan 31, 2023

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A bonding pad such as for a ball grid array includes a conductive pad having a top surface and a first interface surface in contact with a signal trace of a substrate, and a plating layer having a bottom surface in direct contact with the top surface of the conductive pad. The plating layer includes one or more protrusions extending toward the signal trace in a direction generally parallel to a longitudinal axis of the signal trace. Each of the one or more protrusions includes two parallel sidewalls extending upwardly from the bottom surface of the plating layer, and a second interface surface contiguous with the bottom surface of the plating layer. The second interface surface is positioned over and in direct contact with a top surface of the signal trace. The protrusions prevent the connection to the signal trace from being compromised.

First claim

Opening claim text (preview).

What is claimed is: 1. A bonding pad, comprising: a conductive pad having a first interface surface in contact with a signal trace of a substrate; and a plating layer having a bottom surface in direct contact with the conductive pad, and one or more protrusions extending toward the signal trace in a direction generally parallel to a longitudinal axis of the signal trace, the one or more protrusions having a width extending in a direction perpendicular to the longitudinal axis and which is less than a width of the signal trace, and wherein the one or more protrusions extend into one or more apertures defined by a solder mask of the substrate, wherein each of the one or more protrusions include two parallel sidewalls extending upwardly from the bottom surface of the plating layer, and a second interface surface contiguous with the bottom surface of the plating layer, the second interface surface being disposed over and in direct contact with a top surface of the signal trace. 2. The bonding pad of claim 1 , wherein the plating layer is a nickel-gold plating layer. 3. The bonding pad of claim 1 , wherein the one or more protrusions includes a first protrusion and a second protrusion. 4. The bonding pad of claim 3 , wherein the first protrusion and second protrusion extend outwardly from the plating layer generally parallel to one another. 5. The bonding pad of claim 3 , wherein the first protrusion and second protrusion extend outwardly from the plating layer at generally the same length. 6. The bonding pad of claim 3 , wherein the first protrusion and second protrusion extend outwardly from the plating layer at unequal lengths. 7. The bonding pad of claim 3 , wherein the first protrusion and second protrusion are symmetric about the longitudinal axis. 8. The bonding pad of claim 3 , wherein the first protrusion has a width extending in a direction perpendicular to the longitudinal axis and second protrusion has a width extending in a direction perpendicular to the longitudinal axis, wherein a combined width of the first protrusion and second protrusion is less than a width of the signal trace. 9. The bonding pad of claim 1 , wherein the one or more protrusions have a generally rectangular cross-sectional shape. 10. The bonding pad of claim 1 , wherein a top surface of the one or more protrusions is covered by a solder mask of the substrate. 11. A substrate bonding pad, comprising: conducting means for electrically coupling a solder ball to a trace of the substrate, the conducting means having a first interface means for electrically connecting to the trace; and plating means covering a surface of the conducting means for protecting the conducting means from corrosion and/or providing strength to the conducting means, the plating means electrically coupling the solder ball to the conducting means, the plating means having protrusion means for directly contacting the trace, the protrusion means having a second interface means for electrically connecting to the trace separate and distinct from the first interface means, wherein the protrusion means having a width extending in a direction perpendicular to a longitudinal axis of the trace and which is less than a width of the trace, and wherein the protrusion means extend into one or more apertures defined by a solder mask means of the substrate. 12. The substrate bonding pad of claim 11 , wherein the plating means comprises a first plating means and a second plating means for directly contacting the trace of the substrate with second and third interface surface areas respectively. 13. The substrate bonding pad of claim 12 , wherein the second and third interface surface areas are equal. 14. The substrate bonding pad of claim 12 , wherein the second and third interface surface areas are unequal. 15. A substrate, comprising: an insulating layer configured to provide electrical insulation between electrically conductive elements of the substrate; a signal trace coupled to a top surface of the insulating layer; a solder mask in direct contact with a top surface of the signal trace, the solder mask defining a solder mask opening; and a bonding pad positioned within the solder mask opening, the bonding pad configured to directly contact the signal trace within two or more interface surface areas, the two or more interface surface areas being separate and distinct from one another, the bonding pad comprising: a conductive pad having a first interface surface in contact with a signal trace of the substrate; and a plating layer having a bottom surface in direct contact with the conductive pad, and one or more protrusions extending toward the signal trace in a direction generally parallel to a longitudinal axis of the signal trace, the one or more protrusions having a width extending in a direction perpendicular to the longitudinal axis and which is less than a width of the signal trace, and wherein the one or more protrusions extend into one or more apertures defined by a solder mask of the substrate, wherein each of the one or more protrusions include two parallel sidewalls extending upwardly from the bottom surface of the plating layer, and a second interface surface contiguous with the bottom surface of the plating layer, the second interface surface being disposed over and in direct contact with a top surface of the signal trace. 16. The substrate of claim 15 , wherein the solder mask opening includes one or more apertures configured to receive the one or more protrusions of the bonding pad. 17. The substrate of claim 15 , wherein the one or more protrusions includes a first protrusion and a second protrusion spaced from one another in a direction perpendicular to the longitudinal axis. 18. The substrate of claim 15 , wherein a top surface of the one or more protrusions is covered by the solder mask.

Assignees

Inventors

Classifications

  • Electricity · mapped topic

  • Coating free areas, e.g. areas other than pads or lands free of solder resist · CPC title

  • Pads for surface mounting, e.g. lay-out · CPC title

  • Ball grid array [BGA]; Bump grid array · CPC title

  • Electricity · mapped topic

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What does patent US11569155B2 cover?
A bonding pad such as for a ball grid array includes a conductive pad having a top surface and a first interface surface in contact with a signal trace of a substrate, and a plating layer having a bottom surface in direct contact with the top surface of the conductive pad. The plating layer includes one or more protrusions extending toward the signal trace in a direction generally parallel to a…
Who is the assignee on this patent?
Western Digital Tech Inc
What technology area does this patent fall under?
Primary CPC classification H01L23/49811. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jan 31 2023 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).