Semiconductor package and method of forming the same

Patent metadata

Field	Value
Publication number	US-11569146-B2
Application number	US-201716312987-A
Country	US
Kind code	B2
Filing date	Jun 8, 2017
Priority date	Jun 24, 2016
Publication date	Jan 31, 2023
Grant date	Jan 31, 2023

Abstract

Various embodiments may provide a semiconductor package. The semiconductor package may include a semiconductor chip, a first mold compound layer at least partially covering the semiconductor chip, and a redistribution layer over the first mold compound layer, the redistribution layer including one or more electrically conductive lines in electrical connection with the semiconductor chip. The semiconductor package may additionally include a second mold compound layer over the redistribution layer, and an antenna array over the second mold compound layer, the antenna array configured to be coupled to the one or more electrically conductive lines.

First claim

What is claimed is:

1. A semiconductor package comprising:
a semiconductor chip;
a first mold compound layer at least partially covering the semiconductor chip;
a redistribution layer over the first mold compound layer, the redistribution layer comprising one or more electrically conductive lines in electrical connection with the semiconductor chip;
a second mold compound layer over the redistribution layer; and
an antenna array over the second mold compound layer, the antenna array configured to be coupled to the one or more electrically conductive lines;
a thermal cooling structure in thermal contact with the semiconductor chip, the coupling between the one or more electrically conductive lines and the antenna array being inductive coupling or capacitive coupling;
wherein the antenna array is physically isolated from the one or more electrically conductive lines;
wherein the semiconductor chip is configured to transmit one or more first electrical signals to the one or more conductive lines so that the antenna array emit one or more first wireless signals in response to the one or more first electrical signals;
wherein the semiconductor chip is further configured to receive one or more second electrical signals from the one or more first conductive lines in response to the antenna array receiving one or more second wireless signals;
wherein the semiconductor chip comprises one or more die electrical contacts on a first planar surface of the semiconductor chip;
wherein the one or more electrically conductive lines are in contact with the one or more die electrical contacts;
wherein the thermal cooling structure is in contact with a second planar surface of the semiconductor chip opposite the first planar surface;
wherein the redistribution layer comprises a plurality of further electrically conductive lines;
wherein the semiconductor package further comprises a plurality of mold layer electrical contacts on a first surface of the first mold compound layer opposite a second surface of the first mold compound layer in contact with the redistribution layer; and
wherein the semiconductor package also comprises one or more through mold vias extending from the first surface of the first mold compound layer to the second surface of the first mold compound layer, the one or more through mold vias configured to electrically couple the plurality of further electrically conductive lines with the one or more mold layer electrical contacts.

2. The semiconductor package according to claim 1 ,
wherein the thermal cooling structure comprises a plurality of contact fins in contact with the semiconductor chip.

3. The semiconductor package according to claim 2 ,
wherein the thermal cooling structure further comprises a plurality of convection fins in thermal contact with the plurality of the contact fins.

4. The semiconductor package according to claim 3 ,
wherein the thermal cooling structure further comprises a lateral plate having a first surface in contact with the plurality of contact fins, and a second surface in contact with the plurality of convection fins.

5. The semiconductor package according to claim 4 ,
wherein the thermal cooling structure further comprises one or more spreading pads in thermal contact with the plurality of the convection fins.

6. The semiconductor package according to statement 5 ,
wherein the one or more spreading pads extend substantially perpendicular to the plurality of convection fins.

7. The semiconductor package according to claim 2 ,
wherein the thermal cooling structure further comprises a thermal filler between the plurality of contact fins.

8. The semiconductor package according to claim 1 ,
wherein the redistribution layer further comprises one or more dielectric layers at least partially covering the one or more electrically conductive lines.

9. The semiconductor package according to claim 1 , further comprising:
a substrate; and
one or more solder elements, each solder element connecting one of the one or more mold layer electrical contacts with the substrate.

10. The semiconductor package according to claim 1 , further comprising:
wherein the redistribution layer comprises one or more ground plates in electrical connection with one or more of the plurality of further electrically conductive lines.

11. The semiconductor package according to claim 10 ,
wherein each of the one or more ground plates comprises an aperture.

12. The semiconductor package according to claim 11 ,
wherein the antenna array comprises a plurality of patch elements; and
wherein the aperture is over a corresponding electrically conductive line of the plurality of conductive lines so that the aperture is between the corresponding electrically conductive line and a corresponding patch element of the plurality of patch elements.

13. The semiconductor package according to claim 12 ,
wherein a distance between the corresponding electrically conductive line and a plane formed by the ground plate is less than 10 μm.

14. The semiconductor package according to claim 1 ,
wherein a thickness of the second mold compound layer is more than 50 μm.

15. A method of forming a semiconductor package, the method comprising:
providing a semiconductor chip;
forming a first mold compound layer at least partially covering the semiconductor chip;
forming a redistribution layer over the first mold compound layer, the redistribution layer comprising one or more electrically conductive lines in electrical connection with the semiconductor chip;
forming a second mold compound layer over the redistribution layer;
forming an antenna array over the second mold compound layer, the antenna array configured to be coupled to the one or more electrically conductive lines, the coupling between the one or more electrically conductive lines and the antenna array being inductive coupling or capacitive coupling; and
providing a thermal cooling structure in thermal contact with the semiconductor chip;
wherein the antenna array and the thermal cooling structure are provided on different sides of the package;
wherein the antenna array is physically isolated from the one or more electrically conductive lines;
wherein the semiconductor chip is configured to transmit one or more first electrical signals to the one or more conductive lines so that the antenna array emit one or more first wireless signals in response to the one or more first electrical signals;
wherein the semiconductor chip is further configured to receive one or more second electrical signals from the one or more first conductive lines in response to the antenna array receiving one or more second wireless signals;
wherein the redistribution layer comprises a plurality of further electrically conductive lines;
wherein the semiconductor package further comprises a plurality of mold layer electrical contacts on a first surface of the first mold compound layer opposite a second surface of the first mold compound layer in contact with the redistribution layer; and
wherein the semiconductor package also comprises one or more through mold vias extending from the first surface of the first mold compound layer to the second surface of the first mold compound layer, the one or more through mold vias configured to electrically couple the plurality of further electrically conductive lines with the one or more mold layer electrical contacts.

Assignees

• Agency Science Tech & Res

Inventors

• Chang Ka Fai
• Han Yong
• Ho David Soon Wee
• Lim Ying Ying

Classifications

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W72/874

  On different surfaces · CPC title

• H10W72/9413

  on encapsulations · CPC title

• H10W72/0198

  batch processes · CPC title

• H01L23/3672 Primary

  Electricity · mapped topic