Semiconductor device

Patent metadata

Field	Value
Publication number	US-11569128-B2
Application number	US-202117174409-A
Country	US
Kind code	B2
Filing date	Feb 12, 2021
Priority date	Sep 20, 2018
Publication date	Jan 31, 2023
Grant date	Jan 31, 2023

Abstract

A semiconductor device includes a substrate including an active pattern, a first interlayer dielectric layer on the substrate, the first interlayer dielectric layer including a recess on an upper portion thereof, and a lower connection line in the first interlayer dielectric layer, the lower connection line being electrically connected to the active pattern, and the lower connection line including a conductive pattern, the recess of the first interlayer dielectric layer selectively exposing a top surface of the conductive pattern, and a barrier pattern between the conductive pattern and the first interlayer dielectric layer, the first interlayer dielectric layer covering a top surface of the barrier pattern.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a substrate including a plurality of active fins;
a device layer on the substrate and between adjacent ones of the plurality of active fins;
at least one source/drain pattern on the plurality of active fins;
an active contact on the at least one source/drain pattern, the active contact being connected to the at least one source/drain pattern;
a via on the active contact, the via being electrically connected to the active contact;
a first lower connection line and a second lower connection line above the via, the first lower connection line being connected to the via, and the second lower connection line being adjacent to the first lower connection line;
an etch stop layer on the first and second lower connection lines;
an upper connection line on the etch stop layer, the upper connection line being connected to the first lower connection line through a vertical extension part of the upper connection line,
wherein the vertical extension part of the upper connection line penetrates the etch stop layer,
wherein the etch stop layer extends from a sidewall of the vertical extension part to a top surface of the second lower connection line, and
wherein the etch stop layer includes a stepwise structure on an edge of the top surface of the second lower connection line.

2. The semiconductor device as claimed in claim 1 , wherein:
the etch stop layer further includes a first portion on the sidewall of the vertical extension part, and a second portion on the top surface of the second lower connection line, and
a bottom surface of the first portion is higher than a bottom surface of the second portion.

3. The semiconductor device as claimed in claim 1 , wherein each of the first and second lower connection lines and the upper connection line includes a barrier pattern and a conductive pattern on the barrier pattern.

4. The semiconductor device as claimed in claim 1 , further comprising a first interlayer dielectric layer on the substrate, wherein:
the first and second lower connection lines are in the first interlayer dielectric layer,
the first interlayer dielectric layer includes a first recess and a second recess that are on an upper portion of the first interlayer dielectric layer,
the first recess exposes a top surface of the first lower connection line,
the second recess exposes the top surface of the second lower connection line,
the vertical extension part fills the first recess, and
the etch stop layer partially fills the second recess.

5. The semiconductor device as claimed in claim 4 , wherein:
the vertical extension part includes a first segment on the top surface of the first lower connection line, and a second segment on the first interlayer dielectric layer, and
the first segment protrudes more than the second segment toward the substrate.

6. The semiconductor device as claimed in claim 4 , wherein a top surface of the first interlayer dielectric layer is higher than the top surface of the second lower connection line.

7. The semiconductor device as claimed in claim 4 , further comprising a liner between the first interlayer dielectric layer and the plurality of lower connection lines, a top surface of the liner adjacent to the second recess being higher than the top surface of the second lower connection line.

8. The semiconductor device as claimed in claim 4 , wherein the first interlayer dielectric layer further includes an air gap between the first and second lower connection lines.

9. The semiconductor device as claimed in claim 1 , wherein the first and second lower connection lines extend in a first direction, and the upper connection line extends in a second direction intersecting the first direction.

10. The semiconductor device as claimed in claim 1 , wherein the etch stop layer covers at least a portion of the sidewall of the vertical extension part, and the etch stop layer covers at least a portion of the top surface of the second lower connection line.

11. A semiconductor device, comprising:
a substrate including a plurality of active fins;
a device layer on the substrate and between adjacent ones of the plurality of active fins;
at least one source/drain pattern on the plurality of active fins;
an active contact on the at least one source/drain pattern, the active contact being connected to the at least one source/drain pattern;
a first interlayer dielectric layer on the substrate, a top surface of the first interlayer dielectric layer being substantially coplanar with a top surface of the active contact;
a via on the active contact, the via being electrically connected to the active contact;
a second interlayer dielectric layer on the first interlayer dielectric layer;
a first lower connection line connected to the via and a second lower connection line adjacent to the first lower connection line, the first and second lower connection lines being in the second interlayer dielectric layer;
an etch stop layer on the second interlayer dielectric layer;
a third interlayer dielectric layer on the etch stop layer; and
an upper connection line in the third interlayer dielectric layer, the upper connection line being connected to the first lower connection line through a vertical extension part of the upper connection line,
wherein the second interlayer dielectric layer includes a first recess and a second recess that are on an upper portion of the second interlayer dielectric layer,
wherein the first recess exposes a top surface of the first lower connection line,
wherein the second recess exposes a top surface of the second lower connection line,
wherein the vertical extension part fills the first recess,
wherein the etch stop layer partially fills the second recess, and
wherein the etch stop layer includes a stepwise structure formed by the second recess.

12. The semiconductor device as claimed in claim 11 , wherein:
the etch stop layer further includes a first portion on a top surface of the second interlayer dielectric layer, and a second portion on the top surface of the second lower connection line, and
a bottom surface of the first portion is higher than a bottom surface of the second portion.

13. The semiconductor device as claimed in claim 12 , wherein the stepwise structure of the etch stop layer connects the first portion to the second portion.

14. The semiconductor device as claimed in claim 11 , wherein each of the first and second lower connection lines and the upper connection line includes a barrier pattern and a conductive pattern on the barrier pattern.

15. The semiconductor device as claimed in claim 11 , wherein:
the vertical extension part includes a first segment on the top surface of the first lower connection line, and a second segment on the second interlayer dielectric layer, and
the first segment protrudes more than the second segment toward the substrate.

16. The semiconductor device as claimed in claim 11 , wherein a top surface of the first interlayer dielectric layer is higher than the top surface of the second lower connection line.

17. The semiconductor device as claimed in claim 11 , further comprising a liner between the second interlayer dielectric layer and the first and second lower connection lines, a top surface of the liner adjacent to the second recess being higher than the top surface of the second lower connection line.

18. The semiconductor device as claimed in claim 11 , wherein the second interlayer dielectric layer further includes an air gap between the first and second lower con

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Woojin
• Seo Hoon Seok
• Ahn Sanghoon
• Han Kyu-Hee

Classifications

• H10W20/0693

  by forming self-aligned vias · CPC title

• H01L23/5283

  Electricity · mapped topic

• H01L21/76897 Primary

  Electricity · mapped topic

• H01L21/76834

  Electricity · mapped topic

• H01L21/7682

  Electricity · mapped topic