CMOS active inductor circuit for amplifier

Patent metadata

Field	Value
Publication number	US-11568923-B1
Application number	US-202117352938-A
Country	US
Kind code	B1
Filing date	Jun 21, 2021
Priority date	Jun 21, 2021
Publication date	Jan 31, 2023
Grant date	Jan 31, 2023

Abstract

A device, a memory interface device, and a method of implementing an active inductor circuit are disclosed. In one aspect, the device includes one or more active inductor circuits, each including a first metal-oxide-semiconductor (MOS) transistor and a second MOS transistor. The first MOS transistor has a first terminal connected to a first voltage level, a second terminal connected to a resistor, and a gate terminal. The second MOS transistor has a first terminal connected to the first voltage level, a second terminal connected to a first current source and the gate terminal of the first MOS transistor, and a gate terminal connected to the resistor and to a capacitor connected to a second voltage level. One of the first MOS transistor and the second MOS transistor is a p-channel MOS (PMOS) transistor, and another of the first MOS transistor and the second MOS transistor is an n-channel MOS (NMOS) transistor.

First claim

What is claimed is:

1. A device comprising:
one or more active inductor circuits, each comprising:
a first metal-oxide-semiconductor (MOS) transistor having:
a first terminal connected to a first voltage level;
a second terminal connected to a resistor, and
a gate terminal; and

a second MOS transistor having:
a first terminal connected to the first voltage level,
a second terminal connected to a first current source and the gate terminal of the first MOS transistor, and
a gate terminal connected to the resistor, and to a capacitor connected to a second voltage level,

wherein one of the first MOS transistor and the second MOS transistor is a p-channel MOS (PMOS) transistor, and another of the first MOS transistor and the second MOS transistor is a n-channel MOS (NMOS) transistor.

2. The device of claim 1 , further comprising:
an amplifier comprising:
a first active inductor circuit of the one or more active inductor circuits,
a third MOS transistor,
an input connected to a gate terminal of the third MOS transistor, and
an output connected to the second terminal of the first MOS transistor of the first active inductor circuit, and to a first terminal of the third MOS transistor.

3. The device of claim 1 , further comprising:
a first differential amplifier comprising:
a first active inductor circuit of the one or more active inductor circuits; and
a second active inductor circuit of the one or more active inductive circuits.

4. The device of claim 3 , wherein the first differential amplifier further comprises:
a third MOS transistor having:
a first terminal connected to a first output of the first differential amplifier, and to the resistor of the first active inductor circuit;
a second terminal connected to a second current source connected to the second voltage level; and
a gate terminal connected to a first input of the first differential amplifier; and

a fourth MOS transistor having:
a first terminal connected to a second output of the first differential amplifier, and to the resistor of the second active inductor circuit;
a second terminal connected to a third current source connected to the second voltage level; and
a gate terminal connected to a second input of the first differential amplifier.

5. The device of claim 4 , wherein the first differential amplifier further comprises:
a programmable continuous time linear equalizer (CTLE) connected to the second terminal of the third MOS transistor and the second terminal of the fourth MOS transistor.

6. The device of claim 5 , further comprising a second differential amplifier, the second differential amplifier comprising:
a third active inductor circuit of the one or more active inductor circuits;
a fifth MOS transistor having:
a first terminal connected to a first output of the second differential amplifier, and to the resistor of the third active inductor circuit;
a second terminal connected to a fourth current source connected to the second voltage level; and
a gate terminal connected to the first output of the first differential amplifier;

a fourth active inductor circuit of the one or more active inductor circuits; and
a sixth MOS transistor having:
a first terminal connected to a second output of the second differential amplifier, and to the resistor of the fourth active inductor circuit;
a second terminal connected to the fourth current source; and
a gate terminal connected to the second output of the first differential amplifier.

7. The device of claim 6 , further comprising a third differential amplifier, the third differential amplifier comprising:
a fifth active inductor circuit of the one or more active inductor circuits;
a seventh MOS transistor having:
a first terminal connected to a first output of the third differential amplifier, and to the resistor of the fifth active inductor circuit;
a second terminal connected to a fifth current source connected to the second voltage level; and
a gate terminal connected to the first output of the second differential amplifier;

a sixth active inductor circuit of the one or more active inductor circuits; and
a eighth MOS transistor having:
a first terminal connected to a second output of the third differential amplifier, and to the resistor of the sixth active inductor circuit;
a second terminal connected to the fifth current source; and
a gate terminal connected to the second output of the second differential amplifier.

8. The device of claim 7 , wherein the device is included in a graphics double data rate 6 (GDDR6) synchronous dynamic random access memory (SDRAM) device.

9. The device of claim 8 , wherein the GDDR6 SDRAM device comprises:
a receiver comprising the first to third differential amplifiers; and
one or more sampler circuits having first and second inputs,
wherein the first and second outputs of the third differential amplifier are respectively connected to the first and second inputs of the one or more sampler circuits.

10. The device of claim 1 , wherein the first voltage level comprises a first power supply voltage (VDD), a second power supply voltage (VSS), ground or 0 volts.

11. The device of claim 1 , wherein the second voltage level comprises a first power supply voltage (VDD), a second power supply voltage (VSS), ground or 0 volts.

12. A memory interface device, comprising:
a receiver configured to receive an input signal and comprising:
a first amplifier comprising:
a first input transistor configured to receive the input signal; and
a first active inductor circuit of one or more active inductor circuits, each active inductor circuit comprising:
a first transistor having:
 a first terminal connected to a first voltage level;
 a second terminal connected to a first output, the input transistor, and a resistor, and
 a gate terminal; and
a second transistor having:
 a first terminal connected to the first voltage level,
 a second terminal connected to a first current source and the gate terminal of the first transistor, and
 a gate terminal connected to the resistor, and to a capacitor connected to a second voltage level;

a second amplifier comprising a second active inductor circuit of the one or more active inductor circuits, wherein the second amplifier is connected to the first output of the first amplifier;
a third amplifier comprising a third active inductor circuit of the one or more active inductor circuits, wherein the third amplifier is connected to the first output of the second amplifier; and
one or more samplers connected to the output of the third amplifier and configured to output an output signal.

13. The memory interface device of claim 12 , further comprising:
at least one double data rate (DDR) synchronous dynamic random access memory (SDRAM) device connected to the one or more samplers to receive the output signal.

14. The memory interface device of claim 13 , wherein the at least one DDR SDRAM device includes at least one graphics double data rate 6 (GDDR6) SDRAM device.

15. The memory interface device of claim 12 , wherein one of the first transistor and the second transistor is a p-channel metal-oxide-semiconductor (PMOS) transistor, and another of the first transistor and the second transistor is an n-channel metal-oxide-semiconductor (NMOS) transistor.

16. The memory interface device of claim 12 , wherein the first amplifier further comprises:
a second input transistor configured to receive the input signal;
a fourth active inductor circuit of the one or more active inductor circuits, wherein the fourth active inductor circ

Assignees

• Cadence Design Systems Inc

Inventors

• Fazeel Hajee Mohammed Shuaeb
• Kumar Vinod

Classifications

• G11C11/4093 Primary

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• H03F3/45269

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• H03F2200/372

  Noise reduction and elimination in amplifier · CPC title

• H03F2203/45534

  the FBC comprising multiple switches and being coupled between the LC and the IC · CPC title

• H03F2203/45494

  the CSC comprising one or more potentiometers · CPC title