Floorplan of a design for an integrated circuit

Patent metadata

Field	Value
Publication number	US-11568633-B2
Application number	US-202016815248-A
Country	US
Kind code	B2
Filing date	Mar 11, 2020
Priority date	Mar 11, 2020
Publication date	Jan 31, 2023
Grant date	Jan 31, 2023

Abstract

A computer-implemented method for comparing a first version of a floorplan of a design for an integrated circuit with a second version. The method comprises (i) generating a timing information for each net in the second version by determining whether timing information is available for the net in the first version; (ii) in case no timing information is available in the first version, generating the timing information for the second version by calculating a spatial distance and timing information between two points of the net using wire length differences between the first version and the second version; (iii) otherwise, generating the timing information for the second version by calculating a spatial distance and timing information between two points of the net using a wire reach table to obtain a wire delay.

First claim

The invention claimed is:

1. A computer-implemented method for comparing a first version of a floorplan of a design for an integrated circuit with a second version, wherein wires of the electronic circuit are represented as nets in a netlist and wherein the first version comprises timing information representing net delay values as a function of a wire length or a wire constraint of signal paths, and wherein the second version is a modification of the first version, the method comprising:
generating timing information for each net in the second version by determining whether timing information is available for the net in the first version;
in response to timing information being unavailable in the first version, generating timing information for the second version by calculating a spatial distance and timing information between two points of the net using wire length differences between the first version and the second version; and
in response to the timing information being available for the first version, generating timing information for the second version by calculating a spatial distance and timing information between two points of the net using a wire reach table to obtain a wire delay, wherein the second version of the floorplan is optimized based by minimizing the sum of net delay values as a function of a wire length or a wire constraint of signal paths; and
selecting either said first or second version based on improvements on either timing and/or distance.

2. The method according to claim 1 , wherein the second version of the floorplan is a modification of the first version without timing information of the first version.

3. The method according to claim 1 , wherein the timing information generated for the second version comprises at least a classification for the net in comparison with the first version.

4. The method according to claim 1 , wherein the timing information generated for the second version is used to determine whether a predefined timing criterion is met for the second version.

5. The method according to claim 4 , wherein the timing criterion comprises a figure of merit representing a sum of net delay values as a function of a wire length or a wire constraint of signal paths.

6. The method according to claim 5 , wherein the second version of the floorplan is optimized based on the figure of merit.

7. The method according to claim 5 , wherein the figure of merit comprises a sum of negative values of arrival times of a signal at any point in the floorplan required to meet a timing criterion.

8. The method according to claim 1 , wherein calculating a spatial distance and timing information between two points of the net is achieved by calculating a shortest distance between two points of the net using orthogonal branches of the net, in particular by calculating Steiner net lengths.

9. The method according to claim 1 , wherein the net list comprising nets represented by net names comprising wires between a source pin and at least one sink pin, and two-dimensional coordinates of the source pin and the at least one sink pin.

10. The method according to claim 9 , wherein timing information comprises signal arrival times on each source pin and each sink pin.

11. The method according to claim 10 , wherein the signal arrival times are read out from the floorplan of the first version or an additional timing report.

12. The method according to claim 10 , wherein a wire delay value is calculated by subtracting a signal arrival time of a source pin from a signal arrival time at a sink pin.

13. The method according to claim 1 , wherein the wire reach table comprises wire delay values for a wire length of signal paths of the second version compared to a wire length of signal paths of the first version.

14. The method according to claim 1 , wherein timing information for the second version is generated at least for single logic elements of the floorplan.

15. The method according to claim 1 , wherein wires are tagged with net categories according to the determined timing information between two points of the net.

16. The method according to claim 15 , wherein nets of the second version are grouped into buckets according to tagging information.

17. A computer program product for comparing a first version of a floorplan of a design for an integrated circuit with a second version, wherein wires of the electronic circuit are represented as nets in a netlist and wherein the first version comprises timing information representing net delay values as a function of a wire length or a wire constraint of signal paths, and wherein the second version is a modification of the first version, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by a computer system to cause the computer system to perform a method comprising:
generating timing information for each net in the second version by determining whether timing information is available for the net in the first version;
in response to timing information being unavailable in the first version, generating timing information for the second version by calculating a spatial distance and timing information between two points of the net using wire length differences between the first version and the second version; and
in response to the timing information being available for the first version, generating timing information for the second version by calculating a spatial distance and timing information between two points of the net using a wire reach table to obtain a wire delay, wherein the second version of the floorplan is optimized based by minimizing the sum of net delay values as a function of a wire length or a wire constraint of signal paths; and

selecting either said first or second version based on improvements on either timing and/or distance.

18. A data processing system for comparing a first version of a floorplan of a design for an integrated circuit with a second version, wherein wires of the electronic circuit are represented as nets in a netlist and wherein the first version comprises timing information representing net delay values as a function of a wire length or a wire constraint of signal paths, and wherein the second version is a modification of the first version, the data processing system comprising:
one or more computer-readable tangible storage media and program instructions stored on at least one of the one or more tangible storage media, the program instructions executable by a processor of a computer to perform a method, the method comprising:
generating timing information for each net in the second version by determining whether timing information is available for the net in the first version;
in response to timing information being unavailable in the first version, generating timing information for the second version by calculating a spatial distance and timing information between two points of the net using wire length differences between the first version and the second version; and
in response to the timing information being available for the first version, generating timing information for the second version by calculating a spatial distance and timing information between two points of the net using a wire reach table to obtain a wire delay, wherein the second version of the floorplan is optimized based by minimizing the sum of net delay values as a function of a wire length or a wire constraint of signal paths; and

selecting either said first or second version based on improvem

Assignees

• IBM

Inventors

• Schlechter Siegmund
• Beck Manuel

Classifications

• G06V10/757 Primary

  Matching configurations of points or features · CPC title

• G06F30/3312

  Timing analysis · CPC title

• G06F30/398 Primary

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G06F30/392

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• G06F2119/06

  Power analysis or power optimisation · CPC title