Highway jumper to enable long range connectivity for superconducting quantum computer chip

Patent metadata

Field	Value
Publication number	US-11568296-B2
Application number	US-201916711064-A
Country	US
Kind code	B2
Filing date	Dec 11, 2019
Priority date	Dec 11, 2019
Publication date	Jan 31, 2023
Grant date	Jan 31, 2023

Abstract

According to an embodiment of the present invention, a quantum processor includes a qubit chip. The qubit chip includes a substrate, and a plurality of qubits formed on a first surface of the substrate. The plurality of qubits are arranged in a pattern, wherein nearest-neighbor qubits in the pattern are connected. The quantum processor also includes a long-range connector configured to connect a first qubit of the plurality of qubits to a second qubit of the plurality of qubits, wherein the first and second qubits are separated by at least a third qubit in the pattern.

First claim

What is claimed is:

1. A quantum processor, comprising:
a qubit chip, the qubit chip comprising:
a substrate; and
a plurality of qubits formed on a first surface of the substrate, the plurality of qubits arranged in a pattern, wherein nearest-neighbor qubits in the pattern are connected; and
a long-range connector configured to couple a first qubit of the plurality of qubits to a second qubit of the plurality of qubits, wherein the first and second qubits are separated by at least a third qubit in the pattern,

wherein at least a portion of the long-range connector is disposed on a second surface different from said first surface.

2. The quantum processor according to claim 1 , wherein the long-range connector reduces a number of swap gates required for performing two-qubit operations on non-nearest-neighbor qubits.

3. The quantum processor according to claim 1 , wherein the long-range connector is disposed on the first surface of the substrate of the qubit chip.

4. The quantum processor according to claim 1 , wherein the long-range connector is disposed on the second surface, the second surface being a surface of the substrate of the qubit chip, the second surface opposing the first surface.

5. The quantum processor according to claim 4 , wherein the long-range connector comprises:
a first coupling pad arranged to align with the first qubit;
a second coupling pad arranged to align with the second qubit; and
a bus connecting the first coupling pad to the second coupling pad,
wherein, in operation, the first coupling pad capacitively couples to the first qubit and the second coupling pad capacitively couples to the second qubit.

6. The quantum processor according to claim 4 , wherein the long-range connector comprises:
a first coupling coil arranged to align with the first qubit;
a second coupling coil arranged to align with the second qubit; and
a bus connecting the first coupling coil to the second coupling coil,
wherein, in operation, the first coupling coil inductively couples to the first qubit and the second coupling coil inductively couples to the second qubit.

7. The quantum processor according to claim 4 , wherein the long-range connector comprises:
a coupling pad arranged to align with the first qubit;
a coupling coil arranged to align with the second qubit; and
a bus connecting the coupling pad to the coupling coil,
wherein, in operation, the coupling pad capacitively couples to the first qubit and the coupling coil inductively couples to the second qubit.

8. The quantum processor according to claim 1 ,
wherein a first portion of the long-range connector is disposed on the first surface of the substrate of the qubit chip,
wherein a second portion of the long-range connector is disposed on the second surface the second surface being a surface of the substrate of the qubit chip, the second surface opposing the first surface, and
wherein the qubit chip comprises a through via connecting the first portion to the second portion.

9. The quantum processor according to claim 1 , further comprising an interposer chip,
wherein a first portion of the long-range connector is formed on the first surface of the substrate of the qubit chip,
wherein a second portion of the long-range connector is formed on the second surface the second surface being a surface of the interposer chip, and
wherein, in operation, the qubit chip is bonded to the interposer chip such that the first portion of the long-range connector is bonded to the second portion of the long-range connector.

10. The quantum processor according to claim 9 , wherein the interposer chip further comprises a plurality of readout resonators configured to couple to the plurality of qubits formed on the first surface of the substrate of the qubit chip.

11. The quantum processor according to claim 1 , further comprising an interposer chip, wherein the long-range connector is formed on the interposer chip, the long-range connector comprising:
a first coupling pad arranged to align with the first qubit;
a second coupling pad arranged to align with the second qubit; and
a bus connecting the first coupling pad to the second coupling pad,
wherein, in operation, the qubit chip is bonded to the interposer chip such that the first coupling pad capacitively couples to the first qubit and the second coupling pad capacitively couples to the second qubit.

12. The quantum processor according to claim 11 , wherein the interposer chip further comprises a plurality of readout resonators configured to couple to the plurality of qubits formed on the first surface of the substrate of the qubit chip.

13. The quantum processor according to claim 1 , further comprising an interposer chip, wherein the long-range connector is formed on the interposer chip, the long-range connector comprising:
a first coupling coil arranged to align with the first qubit;
a second coupling coil arranged to align with the second qubit; and
a bus connecting the first coupling coil to the second coupling coil,
wherein, in operation, the qubit chip is bonded to the interposer chip such that the first coupling coil inductively couples to the first qubit and the second coupling coil inductively couples to the second qubit.

14. The quantum processor according to claim 1 , further comprising an interposer chip, wherein the long-range connector is formed on the interposer chip, the long-range connector comprising:
a coupling pad arranged to align with the first qubit;
a coupling coil arranged to align with the second qubit; and
a bus connecting the coupling pad to the coupling coil,
wherein, in operation, the qubit chip is bonded to the interposer chip such that the coupling pad capacitively couples to the first qubit and the coupling coil inductively couples to the second qubit.

15. The quantum processor according to claim 1 , wherein the first qubit and the second qubit are located on a perimeter of the pattern.

16. The quantum processor according to claim 1 , wherein the first qubit and the second qubit are separated by at least three qubits in the pattern.

17. An interposer chip, comprising:
a substrate;
a first coupling portion formed on the substrate, the first coupling portion positioned to align with a first qubit on a qubit chip;
a second coupling portion formed on the substrate, the second coupling portion positioned to align with a second qubit on the qubit chip; and
a bus formed on the substrate, the bus connecting the first coupling portion to the second coupling portion,
wherein the first qubit and the second qubit are separated by at least a third qubit,
wherein the interposer chip is configured to be bonded to the qubit chip such that the first coupling portion couples to the first qubit and the second coupling portion couples to the second qubit.

18. The interposer chip according to claim 17 , wherein the first and second coupling portions are first and second coupling pads, and
wherein the interposer chip is configured to be bonded to the qubit chip such that the first coupling pad capacitively couples to the first qubit and the second coupling pad capacitively couples to the second qubit.

19. The interposer chip according to claim 17 , wherein the first and second coupling portions are first and second coupling coils, and
wherein the interposer chip is configured to be bonded to the qubit chip such that the first coupling coil inductively couples to the first qubit and the second coupling coil inductively couples to the second qubit.

Assignees

• IBM

Inventors

• Shao Dongbing
• Brink Markus
• Sandberg Martin O
• Adiga Vivekananda P

Classifications

• H10N69/00

  Integrated devices, or assemblies of multiple devices, comprising at least one superconducting element covered by group H10N60/00 · CPC title

• G06N10/40

  Physical realisations or architectures of quantum processors or components for manipulating qubits, e.g. qubit coupling or qubit control · CPC title

• H01L23/49838

  Electricity · mapped topic

• G06N10/00 Primary

  Quantum computing, i.e. information processing based on quantum-mechanical phenomena · CPC title

• H01L27/18

  Electricity · mapped topic