Quantum controller fast path interface

Patent metadata

Field	Value
Publication number	US-11567887-B2
Application number	US-202017018531-A
Country	US
Kind code	B2
Filing date	Sep 11, 2020
Priority date	Sep 11, 2020
Publication date	Jan 31, 2023
Grant date	Jan 31, 2023

Abstract

Techniques regarding routing qubit data are provided. For example, one or more embodiments described herein can comprise a computer-implemented method for training a quantum controller fast path interface that can control the qubit data routing. The computer-implemented method can comprise training, by a system operatively coupled to a processor, the quantum controller fast path interface for routing qubit data bits between a quantum controller and conditional engine by adjusting a delay value such that a mesochronous clock domain is characterized by a direct register-to-register transfer pattern.

First claim

What is claimed is:

1. A computer-implemented method, comprising:
training, by a system operatively coupled to a processor, a quantum controller fast path interface for routing qubit data bits between a quantum controller and conditional engine by adjusting a delay value such that a mesochronous clock domain is characterized by a direct register-to-register transfer pattern.

2. The computer-implemented method of claim 1 , further comprising:
selecting, by the system, the delay value that stabilizes the mesochronous clock domain by shifting a delay device of the quantum controller fast path interface.

3. The computer-implemented method of claim 2 , wherein the training centers the qubit data bits within the receiving clock domain from active clock edges.

4. The computer-implemented method of claim 3 , wherein the training maximizes a time margin of the receiving clock domain.

5. The computer-implemented method of claim 1 , further comprising:
identifying, by the system, boundaries of a plurality of stable regions of the mesochronous clock domain by tracking a stability of the mesochronous clock domain at a plurality of delay values that the quantum fast path interface can implement with regards to a target wire.

6. The computer-implemented method of claim 5 , the training further comprising:
selecting, by the system, a preferred delay value from the plurality of delay values that is associated with a largest stable region from the plurality of stable regions; and
employing, by the system, the preferred delay value with the target wire for routing the qubit data bits.

7. The computer-implemented method of claim 1 , further comprising:
assessing, by the system, a stability of the mesochronous clock domain at the delay value with regards to a target wire of the quantum controller fast path interface.

8. The computer-implemented method of claim 7 , wherein the assessing comprises:
determining, by the system, whether the target wire is a reference wire of the quantum controller fast path interface based on an assessment that the stability of the mesochronous clock domain is characterized by the direct register-to-register transfer pattern; and
determining, by the system, whether the target wire aligns with the reference wire based on an assessment that the stability of the mesochronous clock domain is characterized by the direct register-to-register transfer pattern.

9. The computer-implemented method of claim 8 , wherein the assessing further comprises:
determining, by the system, whether the qubit data bits are in a stable region of the mesochronous clock domain based on a determination that the target wire is the reference wire or is aligned with the reference wire.

10. A computer program product for routing qubit data bits between a quantum controller and a conditional engine, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by a processor to cause the processor to:
train, by the processor, a quantum controller fast path interface by adjusting a delay value such that a mesochronous clock domain of the quantum controller fast path interface is characterized by a direct register-to-register transfer pattern.

11. The computer program product of claim 10 , wherein the program instructions further cause the processor to:
select, by the processor, a receiving clock domain that stabilizes the mesochronous clock domain by shifting a delay device of the quantum controller fast path interface.

12. The computer program product of claim 10 , wherein the program instructions further cause the processor to:
assess, by the processor, a stability of the mesochronous clock domain at the delay value with regards to a target wire of the quantum controller fast path interface.

13. The computer program product of claim 12 , wherein the program instructions further cause the processor to:
determine, by the processor, whether the target wire is a reference wire of the quantum controller fast path interface based on an assessment that the stability of the mesochronous clock domain is characterized by the direct register-to-register transfer pattern; and
determine, by the processor, whether the target wire aligns with the reference wire based on an assessment that the stability of the mesochronous clock domain is characterized by the direct register-to-register transfer pattern.

14. The computer program product of claim 13 , wherein the program instructions further cause the processor to:
determine, by the processor, whether the qubit data bits are in a stable region of the mesochronous clock domain based on a determination that the target wire is the reference wire or is aligned with the reference wire; and
increase, by the processor, a size of the stable region based on a determination that the qubit data bits are in the stable region.

15. The computer program product of claim 14 , wherein the delay value is from a plurality of delay values to be assessed by the processor, wherein the assessing renders a plurality of stable regions associated with the plurality of delay values with regards to the target wire, and wherein the program instructions further cause the processor to:
select, by the processor, a preferred delay value from the plurality of delay values associated with a largest stable region from the plurality of stable regions; and
employ, by the processor, the preferred delay value with the target wire for routing the qubit data bits.

16. A system, comprising:
a quantum controller fast path interface that routes a qubit data packet between a quantum controller and a conditional engine via a packet transfer protocol in which sender information is inferred from data position within the qubit data packet, wherein the quantum controller broadcasts qubit data to a transmit logic circuitry of the quantum controller fast path interface, and wherein the transmit logic circuitry is synchronized with receive logic circuitry operably coupled to the conditional engine.

17. The system of claim 16 , wherein the transmit logic circuitry cycles through a plurality of routing schemes, and wherein the plurality of routing schemes assign the qubit data packet to a transmission wire from a plurality of transmission wires.

18. The system of claim 16 , wherein the qubit data packet consists of a pairing of the data position and a qubit valid.

19. The system of claim 17 , wherein the packet transfer protocol continuously transfers qubit data between the transmit logic circuitry and the receive logic circuitry while cycling through the plurality of routing schemes.

Assignees

• IBM

Inventors

• Black Ryan
• Greenfield Todd Alan
• Lindquist Timothy

Classifications

• G06F1/12

  Synchronisation of different clock signals {provided by a plurality of clock generators} · CPC title

• G06N10/00

  Quantum computing, i.e. information processing based on quantum-mechanical phenomena · CPC title

• G06F13/3625 Primary

  using a time dependent access · CPC title

• H04L9/0855

  involving additional nodes, e.g. quantum relays, repeaters, intermediate nodes or remote nodes · CPC title

• G06F7/00 Primary

  Methods or arrangements for processing data by operating upon the order or content of the data handled (logic circuits H03K19/00) · CPC title