Method of manufacturing thin film transistor and display device including polishing capping layer coplanar with active layer

Patent metadata

Field	Value
Publication number	US-11563126-B2
Application number	US-202117348188-A
Country	US
Kind code	B2
Filing date	Jun 15, 2021
Priority date	Dec 6, 2018
Publication date	Jan 24, 2023
Grant date	Jan 24, 2023

Abstract

A thin film transistor includes an active layer including a first portion having a first thickness and a second portion having a second thickness greater than the first thickness, a capping layer filling a thickness difference between the first portion and the second portion and arranged on the first portion, a gate insulating layer arranged on the capping layer, a gate electrode on the active layer, wherein the gate insulating layer and the capping layer are disposed between the gate electrode and the active layer, and a source electrode and a drain electrode connected to the active layer.

First claim

What is claimed is:

1. A method of manufacturing a thin film transistor, the method comprising:
forming an amorphous silicon layer over a substrate;
forming a preliminary capping layer on the amorphous silicon layer;
forming a crystalline silicon layer with a protuberance by performing heat treatment on the amorphous silicon layer in which the amorphous silicon layer is liquidized and then the liquidized amorphous silicon layer is crystallized to form the crystalline silicon layer with the protuberance and the preliminary capping layer is deformed to a shape of the protuberance;
polishing the deformed preliminary capping layer and the protuberance to form a capping layer, and an active layer having a first portion having a first thickness and a second portion having a second thickness respectively,
wherein a top surface of the second portion is coplanar with a top surface of the capping layer;
forming a gate insulating layer on the capping layer and the second portion of the active layer;
forming a gate electrode on the gate insulating layer, the gate electrode overlapping the active layer; and
forming a source electrode and a drain electrode that penetrate the capping layer respectively to be connected to the active layer.

2. The method of claim 1 ,
wherein after the polishing of the deformed preliminary capping layer and the protuberance, the protuberance of the crystalline silicon layer is reduced in height to form a preliminary active layer, and the deformed preliminary capping layer is left as a polished deformed preliminary capping layer, and
wherein the preliminary active layer includes:
a first portion, the deformed preliminary capping layer remaining on the first portion as a polished deformed preliminary capping layer; and
a second portion corresponding to the protuberance reduced in height.

3. The method of claim 2 , further comprising:
patterning, after the polishing of the deformed preliminary capping layer and the protuberance of the crystalline silicon layer, the preliminary active layer and the polished deformed preliminary capping layer to form the active layer having a predetermined size, and the capping layer respectively.

4. The method of claim 1 , further comprising:
patterning the amorphous silicon layer to have a predetermined size,
wherein the patterning of the amorphous silicon layer is performed before covering the amorphous silicon layer with the preliminary capping layer, and the preliminary capping layer covers a top surface and a lateral surface of the patterned amorphous silicon layer.

5. The method of claim 1 ,
wherein the gate insulating layer directly contacts the second portion.

6. The method of claim 1 ,
wherein the preliminary capping layer includes silicon oxide.

7. A method of manufacturing a display device, the method comprising:
forming a thin film transistor over a substrate; and
forming a light-emitting element connected to the thin film transistor,
wherein the forming of the thin film transistor comprises:
forming an amorphous silicon layer over the substrate;
forming a preliminary capping layer on the amorphous silicon layer;
forming a crystalline silicon layer with a protuberance by performing heat treatment on the amorphous silicon layer in which the amorphous silicon layer is liquidized and then the liquidized amorphous silicon layer is crystallized to form the crystalline silicon layer with the protuberance and the preliminary capping layer is deformed to a shape of the protuberance;
polishing the deformed preliminary capping layer and the protuberance to form a capping layer, and an active layer including a first portion having a first thickness and a second portion having a second thickness greater than the first thickness respectively, wherein a top surface of the second portion is coplanar with a top surface of the capping layer;
forming a gate insulating layer on the capping layer and the second portion of the active layer;
forming a gate electrode on the gate insulating layer, the gate electrode overlapping the active layer; and
forming a source electrode and a drain electrode that penetrate the capping layer respectively to be connected to the active layer.

8. The method of claim 7 ,
wherein after the polishing of the deformed preliminary capping layer and the protuberance, the protuberance of the crystalline silicon layer is reduced in height to form a preliminary active layer, and the deformed preliminary capping layer is left as a polished deformed preliminary capping layer, and
wherein the preliminary active layer includes:
a first portion, the deformed preliminary capping layer remaining on the first portion as a polished deformed preliminary capping layer; and
a second portion corresponding to the protuberance reduced in height.

9. The method of claim 8 , further comprising:
patterning, after the polishing of the deformed preliminary capping layer and the protuberance of the crystalline silicon layer, the preliminary active layer and the polished deformed preliminary capping layer to from the active layer having a predetermined size, and the capping layer respectively.

10. The method of claim 7 , further comprising:
patterning the amorphous silicon layer to have a predetermined size,
wherein the patterning of the amorphous silicon layer is performed before covering the amorphous silicon layer with the preliminary capping layer, and the preliminary capping layer covers a top surface and a lateral surface of the patterned amorphous silicon layer.

11. The method of claim 7 ,
wherein the gate insulating layer directly contacts the second portion.

12. The method of claim 7 ,
wherein the preliminary capping layer includes silicon oxide.

Assignees

• Samsung Display Co Ltd

Inventors

• Ebisuno Kohei
• Kim Sungjun
• Son Donghyun
• Jung Jaesoo
• Moon Sunghoon
• Jung Jingoo

Classifications

• H10P52/402

  of semiconductor materials · CPC title

• H10P14/69215

  the material being a silicon oxide, e.g. SiO2 · CPC title

• H10P14/3808 Primary

  using laser beams · CPC title

• H10P14/3806

  using crystallisation-enhancing elements · CPC title

• H10P14/3454

  Amorphous · CPC title