Array substrate and manufacturing method thereof, display panel, display device and pixel driving circuit

Patent metadata

Field	Value
Publication number	US-11563073-B2
Application number	US-202017040587-A
Country	US
Kind code	B2
Filing date	Mar 20, 2020
Priority date	Mar 28, 2019
Publication date	Jan 24, 2023
Grant date	Jan 24, 2023

Abstract

Disclosed are an array substrate and a manufacturing method thereof, a display panel, a display device and a pixel driving circuit. The array substrate includes: a base substrate; and a wiring layer and an effective light-emitting layer formed and stacked on the base substrate sequentially, wherein the wiring layer includes a first wiring and a second wiring, an orthographic projection of the first wiring on the base substrate overlaps an orthographic projection of the effective light-emitting layer on the base substrate to form a first overlapping area, an orthographic projection of the second wring on the base substrate overlaps the orthographic projection of the effective light-emitting layer on the base substrate to form a second overlapping area, and the first overlapping area and the second overlapping area are respectively located on both sides of a central line of the orthographic projection of the effective light-emitting layer on the base substrate.

First claim

What is claimed is:

1. An array substrate, comprising:
a base substrate;
a wiring layer and an effective light-emitting layer formed and stacked on the base substrate sequentially;
a planarization layer between the wiring layer and the effective light-emitting layer; and
an interlayer dielectric layer between the base substrate and the wiring layer,
wherein the wiring layer comprises a first wiring and a second wiring, the first wiring and the second wiring are formed on a surface of the interlayer dielectric layer facing away from the base substrate, the second wiring is floating or is connected to an initialization voltage signal, an orthographic projection of the first wiring on the base substrate is overlapped with an orthographic projection of the effective light-emitting layer on the base substrate to form a first overlapping area, an orthographic projection of the second wiring on the base substrate is overlapped with the orthographic projection of the effective light-emitting layer on the base substrate to form a second overlapping area, the orthographic projection of the second wiring on the base substrate is partially overlapped with the second overlapping area, and the first overlapping area and the second overlapping area are respectively located on both sides of a central line of the orthographic projection of the effective light-emitting layer on the base substrate, and
wherein a surface of the planarization layer facing away from the base substrate is in a horizontal state and is substantially parallel to the base substrate.

2. The array substrate according to claim 1 , wherein a distance between the base substrate and a surface of the first wiring facing away from the base substrate is equal to a distance between the base substrate and a surface of the second wiring facing away from the base substrate.

3. The array substrate according to claim 1 , wherein the orthographic projection of the effective light-emitting layer on the base substrate is in an axisymmetric pattern, and the central line of the orthographic projection of the effective light-emitting layer on the base substrate is a symmetry axis of the axisymmetric pattern.

4. The array substrate according to claim 3 , wherein the first overlapping area and the second overlapping area are symmetrically arranged with respect to the central line of the orthographic projection of the effective light-emitting layer on the base substrate.

5. The array substrate according to claim 4 , wherein the first overlapping area and the second overlapping area are both parallel to the central line of the orthographic projection of the effective light-emitting layer on the base substrate.

6. The array substrate according to claim 1 , wherein the wiring layer further comprises a signal line,
wherein a central line of an orthographic projection of the signal line on the base substrate and the central line of the orthographic projection of the effective light-emitting layer on the base substrate are collinear.

7. The array substrate according to claim 6 , wherein the first wiring, the second wiring and the signal line are arranged in the same layer and employ the same material, and the first wiring, the second wiring and the signal line have the same thickness.

8. The array substrate according to claim 7 , wherein the first wiring is a high-voltage power wiring, and the signal line is a data signal line.

9. The array substrate according to claim 1 ,
wherein the planarization layer comprises a first portion and a second portion, an orthographic projection of the first portion on the base substrate coincides with the first overlapping area, an orthographic projection of the second portion on the base substrate coincides with the second overlapping area, and a distance between the base substrate and a surface of the first portion facing away from the base substrate is equal to a distance between the base substrate and a surface of the second portion facing away from the base substrate.

10. The array substrate according to claim 9 , further comprising:
a first electrode between the planarization layer and the effective light-emitting layer,
wherein the first electrode comprises a third portion and a fourth portion, an orthographic projection of the third portion on the base substrate coincides with the first overlapping area, an orthographic projection of the fourth portion on the base substrate coincides with the second overlapping area, a distance between the base substrate and a surface of the third portion facing away from the base substrate is equal to a distance between the base substrate and a surface of the fourth portion facing away from the base substrate, and the third portion and the fourth portion have the same thickness.

11. The array substrate according to claim 10 , wherein the effective light-emitting layer comprises a fifth portion and a sixth portion, an orthographic projection of the fifth portion on the base substrate coincides with the first overlapping area, an orthographic projection of the sixth portion on the base substrate coincides with the second overlapping area, a distance between the base substrate and a surface of the fifth portion facing away from the base substrate is equal to a distance between the base substrate and a surface of the sixth portion facing away from the base substrate, and the fifth portion and the sixth portion have the same thickness.

12. The array substrate according to claim 11 , wherein the fifth portion and the sixth portion are respectively located at two opposite edge regions of the effective light-emitting layer.

13. A display panel comprising the array substrate according to claim 1 .

14. A display device comprising the display panel according to claim 13 .

15. A pixel driving circuit applied to the array substrate according to claim 1 , comprising a first thin film transistor, a second thin film transistor, a third thin film transistor, a fourth thin film transistor, a fifth thin film transistor, a sixth thin film transistor, a seventh thin film transistor, a capacitor, and an organic light-emitting diode, wherein:
a source electrode of the first thin film transistor is connected to an initialization signal, a gate electrode of the first thin film transistor is electrically connected to a reset signal, and a drain electrode of the first thin film transistor is electrically connected to a first node;
a gate electrode of the second thin film transistor is connected to a scan signal, a source electrode of the second thin film transistor is electrically connected to a second node, and a drain electrode of the second thin film transistor is electrically connected to the first node;
a source electrode of the third thin film transistor is electrically connected to the second node, a gate electrode of the third thin film transistor is electrically connected to the first node, and a drain electrode of the third thin film transistor is electrically connected to a third node;
a gate electrode of the fourth thin film transistor is connected to the scan signal, a source electrode of the fourth thin film transistor is electrically connected to a data signal, and a drain electrode of the fourth thin film transistor is electrically connected to the third node;
a source electrode of the fifth thin film transistor is connected to a first power voltage, a gate electrode of the fifth thin film transistor is connected to a light-emitting control signal, and a drain electrode of the fifth thin film transistor is electrically connected to the third node;
a source electrode of the sixth thin film transistor is electrically conn

Assignees

• Boe Technology Group Co Ltd
• Chengdu Boe Optoelect Tech Co

Inventors

• Li Meng
• Du Sen
• Cheng Tianyi
• Zhang Tiaomei
• Huang Yao
• Liu Tingliang

Classifications

• G09G3/3258

  with pixel circuitry controlling the voltage across the light-emitting element · CPC title

• H01L27/3276 Primary

  Electricity · mapped topic

• H01L2227/323

  Electricity · mapped topic

• H10D84/01

  Manufacture or treatment · CPC title

• H10K59/124 Primary

  Insulating layers formed between TFT elements and OLED elements · CPC title