Array substrate and fabrication method thereof, display panel and display module

Patent metadata

Field	Value
Publication number	US-11563036-B2
Application number	US-202016915213-A
Country	US
Kind code	B2
Filing date	Jun 29, 2020
Priority date	Jun 28, 2019
Publication date	Jan 24, 2023
Grant date	Jan 24, 2023

Abstract

The present disclosure provides an array substrate and a fabrication method thereof, a display panel and a display module. The array substrate has a display region and a bonding region for bonding with a circuit board, and including: a data line and a gate line in the display region; and a bump unit in the bonding region. The bump unit includes: a gate line bump layer, which is in a same layer and made of a same material as the gate line, is connected to the data line, and includes a main body portion and a plurality of hollowed-out portions in the main body portion; and a data line bump layer, which is in a same layer and made of a same material as the data line, and covers the main body portion and the plurality of hollowed-out portions of the gate line bump layer.

First claim

The invention claimed is:

1. An array substrate having a display region and a bonding region for bonding with a circuit board, and comprising:
a data line and a gate line in the display region; and
a bump unit in the bonding region, comprising:
a gate line bump layer, which is in a same layer and made of a same material as the gate line, is connected to the data line, and comprises a main body portion and a plurality of hollowed-out portions in the main body portion; and
a data line bump layer, which is in a same layer and made of a same material as the data line, covers the main body portion and the plurality of hollowed-out portions of the gate line bump layer, and comprises a first portion and a second portion, wherein an orthographic projection of the first portion on the gate line bump layer is within the main body portion of the gate line bump layer, an orthographic projection of the second portion on the gate line bump layer is within the hollowed-out portions of the gate line bump layer, and a sum of a thicknesses of the first portion and a thicknesses of the main body portion of the gate line bump layer is larger than a thicknesses of the second portion.

2. The array substrate of claim 1 , wherein the bump unit further comprises a conductive layer covering the data line bump layer on a side of the data line bump layer away from the gate line bump layer,
the conductive layer comprises a third portion and a fourth portion, an orthographic projection of the third portion on the gate line bump layer is within the main body portion of the gate line bump layer and at least partially overlaps with the orthographic projection of the first portion on the gate line bump layer, an orthographic projection of the fourth portion on the gate line bump layer is within the hollowed-out portions of the gate line bump layer and at least partially overlaps with the orthographic projection of the second portion on the gate line bump layer, and a sum of thicknesses of the third portion, the first portion and the main body portion is greater than a sum of thicknesses of the fourth portion and the second portion.

3. The array substrate of claim 2 , wherein the conductive layer is a conductive metal oxide layer.

4. The array substrate of claim 1 , wherein the main body portion comprises a plurality of segments arranged at intervals along an extending direction of the gate line, an interval between any two adjacent segments forms the hollowed-out portion, each segment is strip-shaped, and an angle between a length direction of the segment and an extending direction of the data line is greater than or equal to 0 degree and less than 45 degrees.

5. The array substrate of claim 4 , wherein the plurality of segments are independent of each other and electrically connected to each other through the data line bump layer.

6. The array substrate of claim 4 , wherein the gate line bump layer further comprises a connection portion electrically connecting end portions of the plurality of segments at one side of the gate line bump layer.

7. The array substrate of claim 1 , wherein the main body portion comprises segments arranged in an array in a first direction and a second direction, an interval between any two adjacent segments forms the hollowed-out portion, the first direction is parallel to an extending direction of the gate line, and an angle between the second direction and an extending direction of the data line is greater than or equal to 0 degree and less than 45 degrees.

8. The array substrate of claim 7 , wherein each of the segments has a strip shape, and a length direction of each of the segments is parallel to the second direction.

9. The array substrate of claim 1 , wherein the main body portion comprises a plurality of segments arranged at intervals along a second direction, an interval between any two adjacent segments forms the hollowed-out portion, each segment has a strip shape with a same length, a length direction of the segment is parallel to an extending direction of the gate line, and an angle between the second direction and an extending direction of the data line is greater than or equal to 0 degree and smaller than 45 degrees.

10. The array substrate of claim 1 , wherein the main body portion comprises a plurality of segments arranged at intervals along a second direction, an interval between any two adjacent segments forms the hollowed-out portion, each segment has a strip shape with a same length, an angle between a length direction of the segment and an extending direction of the gate line is greater than or equal to 0 degree and less than 45 degrees, and an angle between the second direction and an extending direction of the data line is greater than or equal to 0 degree and less than 45 degrees.

11. The array substrate of claim 1 , wherein the plurality of hollowed-out portions are a plurality of through holes formed in and penetrating through the main body portion in a thickness direction of the main body portion.

12. The array substrate of claim 11 , wherein the plurality of through holes are arranged in an array in a first direction and a second direction, the first direction is parallel to an extending direction of the gate line, and an angle between the second direction and an extending direction of the data line is greater than or equal to 0 degree and less than 45 degrees.

13. The array substrate of claim 11 , wherein the plurality of through holes are arranged in an array in only one of a first direction and a second direction, the first direction is parallel to an extending direction of the gate line, and an angle between the second direction and an extending direction of the data line is greater than or equal to 0 degree and less than 45 degrees.

14. The array substrate of claim 1 , wherein the bump unit comprises a plurality of gate line bump layers arranged at intervals along a direction parallel to an extending direction of the gate line, each gate line bump layer is connected to one corresponding data line, and the data line bump layer covers all the gate line bump layers.

15. A method of fabricating an array substrate, the array substrate having a display region and a bonding region for bonding with a circuit board, and comprising a data line and a gate line in the display region and a bump unit in the bonding region, wherein the method comprises:
forming a gate line material layer;
performing a patterning process on the gate line material layer to form a pattern comprising the gate line and a gate line bump layer, wherein the gate line bump layer is connected with the data line, and the gate line bump layer is formed to comprise a main body portion and a plurality of hollowed-out portions in the main body portion;
forming a data line material layer on the patterned gate line material layer;
performing a patterning process on the data line material layer to form a pattern comprising the data line and a data line bump layer, wherein the data line bump layer covers the main body portion and the plurality of hollowed-out portions of the gate line bump layer, the data line bump layer is formed to comprise a first portion and a second portion, an orthographic projection of the first portion on the gate line bump layer is within the main body portion of the gate line bump layer, an orthographic projection of the second portion on the gate line bump layer is within the hollowed-out portions of the gate line bump layer, and a sum of a thicknesses of the first portion and a thicknesses of the main body portion of the gate line bump layer is larger than a thickness of the second portion.

16. The

Assignees

• Ordos Yuansheng Optoelectronics Co Ltd
• Boe Technology Group Co Ltd

Inventors

• Han Shuai
• Xu Jingyi
• Zhao Xin
• Tang Wulijibaier
• Ren Yanwei
• Yu Yanan
• Wang Yuelin
• Zhi Guolei

Classifications

• G02F1/136

  Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit (G02F1/135 takes precedence) · CPC title

• H01L27/124 Primary

  Electricity · mapped topic

• H01L24/13

  Electricity · mapped topic

• H01L2224/13562

  Electricity · mapped topic

• H01L2224/13012

  Electricity · mapped topic