Activity detection

Patent metadata

Field	Value
Publication number	US-11558706-B2
Application number	US-202017123801-A
Country	US
Kind code	B2
Filing date	Dec 16, 2020
Priority date	Nov 17, 2017
Publication date	Jan 17, 2023
Grant date	Jan 17, 2023

Abstract

This application relates an activity detector ( 100 ) for detecting signal activity in an input audio signal (S IN ), such as may be used for always-on speech detection. The activity detector has a first time-encoding modulator (TEM) 101 including a first hysteretic comparator ( 201 ) for generating a PWM (pulse-width modulation) signal based on the input audio signal. A second TEM ( 103 ) having a second hysteretic comparator ( 401 ) is arranged to receive a reference voltage (V MID ) and generate a clock signal (S CLK ). A time-decoding converter ( 102 ) receives the clock signal and generates count values of a number of cycles of the clock signal in periods defined by the PWM signal. An activity monitor ( 104 ) is responsive to a count signal (S CT ) from the TDC 102 to determine whether the input audio signal comprises signal activity above a defined threshold.

First claim

The invention claimed is:

1. An activity detector for detecting signal activity in an input audio signal comprising:
a first time-encoding modulator comprising a first hysteretic comparator for generating a PWM (pulse-width modulation) signal based on the input audio signal;
a time-decoding converter configured to receive the PWM signal and a clock signal, and generate count values of a number of cycles of the clock signal in periods defined by the PWM signal and output a count signal based on said count values;
a second time-encoding modulator comprising a second hysteretic comparator for receiving a reference voltage and generating the clock signal with a frequency based on the reference voltage; and
an activity monitor responsive to the count signal to determine whether the input audio signal comprises the signal activity above a defined threshold.

2. The activity detector as claimed in claim 1 wherein the second time-encoding modulator is configurable so as to vary the frequency of the clock signal and wherein the activity detector is configured so as to operate:
in a first mode, with the second time-encoding modulator controlled to generate the clock signal at a first frequency, when the input audio signal comprises no signal activity above the defined threshold; and
in a second mode, with the second time-encoding modulator controlled to generate the clock signal at a second, higher, frequency when the signal activity above the defined threshold is detected.

3. The activity detector as claimed in claim 2 comprising a timing controller for controlling a timing parameter of the first time-encoding modulator in the second mode of operation.

4. The activity detector as claimed in claim 3 wherein said timing parameter of the first time-encoding modulator comprises frequency limits for a maximum and/or a minimum frequency of the PWM signal.

5. The activity detector as claimed in claim 4 wherein said timing controller comprises a first hysteresis controller for controlling hysteresis applied by the first hysteretic comparator wherein, in the second mode of operation, the first hysteresis controller is responsive to the time-decoding converter to control the hysteresis applied by the first hysteretic comparator so as to maintain the frequency of the PWM signal within said frequency limits.

6. The activity detector as claimed in claim 3 wherein the timing parameter comprises the timing of signal transitions in the PWM signal.

7. The activity detector as claimed in claim 6 wherein, in the second mode of operation the timing controller is configured to synchronise any signal transitions in the PWM signal to said clock signal.

8. The activity detector as claimed in claim 7 wherein the first hysteretic comparator comprises a latched hysteretic comparator module and, in the second mode, the timing controller is configured to supply the clock signal to the latched hysteretic comparator module.

9. The activity detector as claimed in claim 1 wherein the reference voltage corresponds to a voltage level of zero signal magnitude of the audio input signal.

10. The activity detector as claimed in claim 1 wherein the second time-encoding modulator comprises a second hysteresis controller for controlling hysteresis applied by the second hysteretic comparator so as to control the frequency of the clock signal.

11. The activity detector as claimed in claim 1 wherein the second time-encoding modulator comprises a loop filter.

12. The activity detector as claimed in claim 11 wherein at least one component of the loop filter of the second time-encoding modulator is configurable so as to vary a time-constant of the loop filter so as to control the frequency of the clock signal.

13. The activity detector as claimed in claim 1 further comprising a buffer configured to receive a version of the count signal from the time-decoding converter, wherein the activity monitor is configured to disable the buffer when the input audio signal comprises no signal activity above the defined threshold and to enable the buffer when the input audio signal comprises the signal activity above the defined threshold.

14. The activity detector as claimed in claim 1 wherein the activity monitor is configured to receive the count signal and monitor a value related to a cycle period of the PWM signal derived from the count signal against a threshold.

15. An audio circuit comprising an activity detector as claimed in claim 1 .

16. The audio circuit as claimed in claim 15 comprising a microphone configured to provide the input audio signal to the activity detector.

17. The audio circuit as claimed in claim 15 comprising an analogue-to-digital converter configured to be enabled by the activity detector when the activity monitor indicates that the input audio signal comprises the signal activity above the defined threshold.

18. The audio circuit as claimed in claim 15 comprising a speech processing module configured to be enabled by the activity detector when the activity monitor indicates that the input audio signal comprises the signal activity above the defined threshold.

19. An activity detector for detecting signal activity in an input audio signal comprising:
a first time-encoding modulator configured to receive the input audio signal as an input and generate a first PWM (pulse-width modulation) signal based on the input audio signal;
a second time-encoding modulator configured to receive a reference voltage and generate a second PWM signal as a clock signal;
a time-decoding converter for counting a number of cycles of the clock signal in periods defined by the first PWM signal;
an activity monitor responsive to the time-decoding converter to determine whether or not the input audio signal comprises the signal activity above a defined threshold.

20. An activity detector for detecting signal activity in an input audio signal comprising:
a first time-encoding modulator configured to generate a PWM (pulse-width modulation) signal based on the input audio signal wherein a cycle period of the PWM signal varies with a magnitude of the input audio signal;
an activity monitor for determining whether the input audio signal comprises the signal activity above a defined threshold based on the cycle period of the PWM signal and,
a timing controller responsive to said activity monitor for controlling a timing parameter of the first time-encoding modulator when the input audio signal comprises the signal activity above the defined threshold; wherein the timing controller is configured to control the timing parameter of the first time-encoding modulator to maintain the cycle period of the PWM signal within defined limits.

Assignees

• Cirrus Logic Int Semiconductor Ltd
• Cirrus Logic Inc

Inventors

• Lesso John Paul

Classifications

• H04R29/004 Primary

  for microphones (H04R29/007 takes precedence) · CPC title

• H03M1/50

  with intermediate conversion to time interval (H03M1/64 takes precedence) · CPC title

• G04F10/005

  Time-to-digital converters [TDC] (analog-to-digital converters with intermediate conversion to time or phase H03M1/50, H03M1/60) · CPC title

• H03M1/508

  the pulse width modulator being of the self-oscillating type · CPC title

• H03M1/002

  Provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains or by selectively turning on stages when needed · CPC title