Reconfigurable analog to digital converter (ADC)

Patent metadata

Field	Value
Publication number	US-11558065-B2
Application number	US-202117158242-A
Country	US
Kind code	B2
Filing date	Jan 26, 2021
Priority date	Jan 26, 2021
Publication date	Jan 17, 2023
Grant date	Jan 17, 2023

Abstract

One example discloses a reconfigurable analog to digital converter (ADC) device, including: an analog front end (AFE) configured to receive a set of analog input signals and generate a corresponding set of digital output signals; wherein the AFE includes a set of reconfigurable ADC conversion circuits; and a sequencer coupled to the AFE and configured to control the set of reconfigurable ADC conversion circuits with a first AFE channel configuration at a first time and a second AFE channel configuration at a second time.

First claim

What is claimed is:

1. A reconfigurable analog to digital converter (ADC) device, comprising:
an analog front end (AFE) configured to receive a set of analog input signals and convert into a corresponding set of digital output signals;
wherein the AFE includes a set of reconfigurable ADC conversion circuits; and
a sequencer coupled to the AFE and configured to control the set of reconfigurable ADC conversion circuits with a first AFE channel configuration at a first time and a second AFE channel configuration at a second time.

2. The device of claim 1 :
wherein the set of reconfigurable ADC conversion circuits include at least one ADC conversion timing circuit reconfigured by at least one of the AFE channel configurations.

3. The device of claim 1 :
wherein the ADC is a sigma-delta converter reconfigured by at least one of the AFE channel configurations.

4. The device of claim 1 :
wherein the sequencer directly controls a set of reconfigurable ADC conversion circuits that control ADC conversion timing.

5. The device of claim 1 :
wherein the sequencer is programmed with the second AFE channel configuration while the sequencer is currently controlling the AFE with the first AFE channel configuration.

6. The device of claim 1 :
wherein the sequencer is programmed to execute multiple different sets of AFE channel configurations in a predetermined sequence.

7. The device of claim 1 :
wherein the sequencer is programmed to execute multiple different sets of AFE channel configurations in an automatically repeating cycle.

8. The device of claim 1 :
wherein the sequencer transitions to a wait state after ADC conversions for the first AFE channel configuration and the second AFE channel configuration are completed; and
wherein after the wait state, the sequencer resumes ADC conversions in response to an external trigger signal received by the sequencer.

9. The device of claim 1 :
wherein the sequencer is programmed to oversample the set of analog input signals with a third AFE channel configuration at a third time; and
wherein the third AFE channel configuration is same as the first AFE channel configuration.

10. The device of claim 1 :
wherein the first and second AFE channel configurations specify a set of AFE timing signals reconfigured by at least one of the AFE channel configurations.

11. The device of claim 10 :
wherein the AFE timing signals include a time delay before start of an ADC conversion.

12. The device of claim 10 :
wherein the AFE timing signals include an ADC conversion data rate.

13. The device of claim 10 :
wherein the AFE timing signals include a chopping rate between at least two different ADC channel conversions.

14. The device of claim 1 :
wherein the first and second channel AFE configurations specify a set of ADC channel gains reconfigured by at least one of the AFE channel configurations.

15. The device of claim 1 :
wherein the first and second channel AFE configurations specify a set of ADC channel filters reconfigured by at least one of the AFE channel configurations.

16. The device of claim 1 :
wherein the first and second channel AFE configurations specify a channel specific set of digital signal under-range thresholds reconfigured by at least one of the AFE channel configurations.

17. The device of claim 1 :
wherein the first and second channel AFE configurations specify a channel specific set of digital signal over-range thresholds reconfigured by at least one of the AFE channel configurations.

18. The device of claim 1 :
wherein the first and second channel AFE configurations specify a set of ADC channel gain calibration coefficients reconfigured by at least one of the AFE channel configurations.

19. The device of claim 1 :
wherein the first and second channel AFE configurations specify a set of ADC offset calibration coefficients reconfigured by at least one of the AFE channel configurations.

20. The device of claim 1 :
wherein the first and second channel AFE configurations specify a set of high or low voltage analog inputs reconfigured by at least one of the AFE channel configurations.

21. The device of claim 1 :
wherein the AFE channel configurations are retrieved from a lookup table.

22. A reconfigurable analog to digital converter (ADC) device, comprising:
an analog front end (AFE) configured to receive a set of analog input signals, a set of channel configuration control signals, and convert into a corresponding set of digital output signals;
wherein the AFE includes a set of reconfigurable ADC conversion circuits;
a sequencer coupled to the AFE and including a channel configuration control signal sequencer table;
wherein the sequencer is configured to control the set of reconfigurable ADC conversion circuits with a first set of channel configuration control signals retrieved from the channel configuration control signal sequencer table at a first time and a second set of channel configuration control signals retrieved from the channel configuration control signal sequencer table at a second time.

Assignees

• Nxp Bv

Inventors

• Le Jean Cauxuan
• Morello Carmelo
• Wong See-Hoi

Classifications

• H03M1/004 Primary

  Reconfigurable analogue/digital or digital/analogue converters (H03M1/02 takes precedence) · CPC title

• H03M3/38

  Calibration · CPC title

• H03M3/458 Primary

  Analogue/digital converters using delta-sigma modulation as an intermediate step · CPC title

• H03M3/472

  Shared, i.e. using a single converter for multiple channels · CPC title

• H03M3/384

  Offset correction (removal of offset already present on the analogue input signal H03M3/494) · CPC title