Battery electrode having network of interconnected high porosity regions and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-11552284-B2
Application number	US-202017084037-A
Country	US
Kind code	B2
Filing date	Oct 29, 2020
Priority date	Oct 29, 2020
Publication date	Jan 10, 2023
Grant date	Jan 10, 2023

Abstract

A battery electrode includes an electrically conductive sheet and two or more coating layers of an ion transport medium stacked thereon. Each coating layer has a respective two-dimensional array of low porosity regions formed therein, with a remainder of each coating layer that is not the two-dimensional array of low porosity regions defining a respective network of interconnected high porosity regions. Each of the high porosity regions has a feature size D, and an intralayer pitch P is defined between adjacent ones of the high porosity regions of each coating layer, with each pair of adjacent two-dimensional arrays having a respective alignment error E therebetween. A respective first electrically conductive path is formed thereacross via the networks of high porosity regions when D≤E≤P, with a second electrically conductive path being formed across all of the coating layers via the networks of high porosity regions.

First claim

What is claimed is:

1. A method of manufacturing a battery electrode, comprising:
applying a coating of an ion transport medium onto a first surface of an electrically conductive sheet;
forming a two-dimensional array of low porosity regions on the coating;
applying a subsequent coating of the ion transport medium onto the previously applied coating; and
forming a subsequent two-dimensional array of low porosity regions on the subsequent coating;
wherein a respective remainder of each coating that is not the respective two-dimensional array of low porosity regions defines a respective network of interconnected high porosity regions, wherein, for each coating, each of the low porosity regions thereof is surroundably bordered by one or more of the high porosity regions thereof;
wherein each of the high porosity regions has a respective feature size D and wherein an intralayer pitch P is defined between adjacent ones of the high porosity regions of each coating, such that each pair of adjacent two-dimensional arrays has a respective alignment error E therebetween and wherein a respective first electrically conductive path is formed thereacross via the respective networks of high porosity regions when D≤E≤P; and
wherein a second electrically conductive path is formed across all of the coatings via the networks of high porosity regions.

2. The method according to claim 1 , wherein each two-dimensional array has substantially the same arrangement of low porosity regions and high porosity regions as each other two-dimensional array.

3. The method according to claim 1 , further comprising:
repeating, for a plurality of cycles, the steps of applying a subsequent coating and forming a subsequent two-dimensional array of low porosity regions.

4. The method according to claim 1 , wherein, for each coating, the low porosity regions thereof have a lower porosity than the high porosity regions thereof.

5. The method according to claim 1 , wherein, for each coating, the low porosity regions thereof have a higher density than the high porosity regions thereof.

6. The method according to claim 1 , wherein the feature size D is a width as measured between adjacent low porosity regions.

7. The method according to claim 1 , wherein each two-dimensional array of low-porosity regions is formed using a stamp or roller having a pattern of embossments on a patterning surface thereof, wherein the embossments are arranged on the patterning surface so as to correspond to each two-dimensional array of low porosity regions.

8. The method according to claim 1 , wherein each of the low porosity regions has a respective tileable shape, wherein each respective tileable shape is one or more of a square, a triangle, a non-square rectangle, a non-rectangular parallelogram, a trapezoid, a hexagon, a rhombus and a cross shape.

9. The method according to claim 1 , wherein each of the low porosity regions has a respective non-tileable shape, wherein each respective non-tileable shape is one or more of a circle, an ellipse, a pentagon, a cloud shape and a star shape.

10. The method according to claim 1 , wherein 0.10≤D/P≤0.50.

11. A method of manufacturing a multilayer battery electrode, comprising:
(i) applying a coating layer of an ion transport medium onto a first surface of an electrically conductive sheet;
(ii) impressing the coating layer so as to form a two-dimensional array of high density impressed regions on a top surface of the coating layer;
(iii) applying a subsequent coating layer of the ion transport medium onto the previously applied coating layer;
(iv) impressing the subsequent coating layer so as to form a subsequent two-dimensional array of high density impressed regions on an exposed surface of the subsequent coating layer; and
(v) repeating steps (iii) and (iv) for a plurality of cycles;
wherein a respective remainder of each coating layer that is not the respective two-dimensional array of high density impressed regions defines a respective network of interconnected low density regions, wherein, for each coating layer, each of the high density impressed regions thereof is surroundably bordered by one or more of the low density regions thereof;
wherein each of the low density regions has a respective feature size D characterized as a width as measured between adjacent high density impressed regions and wherein an intralayer pitch P is defined between adjacent ones of the low density regions of each coating layer, such that each pair of adjacent two-dimensional arrays has a respective alignment error E therebetween, and wherein a respective first electrically conductive path is formed thereacross via the respective networks of low density regions when D≤E≤P; and
wherein a second electrically conductive path is formed across all of the coating layers via the networks of low density regions.

12. The method according to claim 11 , wherein each two-dimensional array has substantially the same arrangement of high density impressed regions and low density regions as each other two-dimensional array.

13. The method according to claim 11 , wherein, for each coating layer, the high density impressed regions thereof have a higher density and a lower porosity than the low density regions thereof.

14. The method according to claim 11 , wherein each of the high density impressed regions has:
a respective tileable shape, wherein each respective tileable shape is one or more of a square, a triangle, a non-square rectangle, a non-rectangular parallelogram, a trapezoid, a hexagon, a rhombus and a cross shape; or
a respective non-tileable shape, wherein each respective non-tileable shape is one or more of a circle, an ellipse, a pentagon, a cloud shape and a star shape.

15. A battery electrode, comprising:
an electrically conductive sheet having a first surface; and
two or more coating layers of an ion transport medium stacked upon the first surface;
wherein each coating layer has a respective two-dimensional array of low porosity impressed regions formed therein, wherein a respective remainder of each coating layer that is not the respective two-dimensional array of low porosity impressed regions defines a respective network of interconnected high porosity regions, wherein, for each coating layer, each of the low porosity impressed regions thereof is surroundably bordered by one or more of the high porosity regions thereof;
wherein each of the high porosity regions has a respective feature size D and wherein an intralayer pitch P is defined between adjacent ones of the high porosity regions of each coating layer, such that each pair of adjacent two-dimensional arrays has a respective alignment error E therebetween, and wherein a respective first electrically conductive path is formed thereacross via the respective networks of high porosity regions when D≤E≤P; and
wherein a second electrically conductive path is formed across all of the coating layers via the networks of high porosity regions.

16. The battery electrode according to claim 15 , wherein each two-dimensional array has substantially the same arrangement of low porosity impressed regions and high porosity regions as each other two-dimensional array.

17. The battery electrode according to claim 15 , wherein, for each coating layer, the feature size D is a width as measured between adjacent low porosity impressed regions, and the low porosity impressed regions thereof have a lower porosity and a higher density than the high porosity regions thereof.

18. The battery electrode according to claim 15 , wherein each of the

Assignees

• Gm Global Tech Operations Llc

Inventors

• Huemiller Erik D

Classifications

• H01M4/0404 Primary

  by coating on electrode collectors · CPC title

• H01M4/13 Primary

  Electrodes for accumulators with non-aqueous electrolyte, e.g. for lithium-accumulators; Processes of manufacture thereof · CPC title

• H01M10/058

  Construction or manufacture · CPC title

• H01M4/043

  involving compressing or compaction · CPC title

• H01M4/139 Primary

  Processes of manufacture · CPC title