High voltage double-diffused metal oxide semiconductor transistor with isolated parasitic bipolar junction transistor region

Patent metadata

Field	Value
Publication number	US-11552190-B2
Application number	US-202016952500-A
Country	US
Kind code	B2
Filing date	Nov 19, 2020
Priority date	Dec 12, 2019
Publication date	Jan 10, 2023
Grant date	Jan 10, 2023

Abstract

A modified structure of an n-channel lateral double-diffused metal oxide semiconductor (LDMOS) transistor is provided to suppress the rupturing of the gate-oxide which can occur during the operation of the LDMOS transistor. The LDMOS transistor comprises a dielectric isolation structure which physically isolates the region comprising a parasitic NPN transistor from the region generating a hole current due to weak-impact ionization, e.g., the extended drain region of the LDMOS transistor. According to an embodiment of the disclosure, this can be achieved using a vertical trench between the two regions. Further embodiments are also proposed to enable a reduction in the gain of the parasitic NPN transistor and in the backgate resistance in order to further improve the robustness of the LDMOS transistor.

First claim

What is claimed is:

1. A lateral double-diffused metal oxide semiconductor (LDMOS) transistor comprising:
a drain;
a gate;
a source; and
a backgate,
wherein the LDMOS transistor further comprises an oxide-filled trench isolation structure configured to physically isolate a first region comprising the drain of the LDMOS transistor from a second region comprising the source of the LDMOS transistor, the second region having a parasitic bipolar junction transistor.

2. The LDMOS transistor according to claim 1 , wherein the LDMOS transistor comprises an n-channel LDMOS transistor, and wherein the parasitic bipolar junction transistor comprises a parasitic NPN bipolar junction transistor.

3. The LDMOS transistor according to claim 1 , wherein the LDMOS transistor comprises a p-channel LDMOS transistor and wherein the parasitic bipolar junction transistor comprises a parasitic PNP bipolar junction transistor.

4. The LDMOS transistor according to claim 1 , wherein the gate comprises a polysilicon-on-oxide structure in the second region.

5. The LDMOS transistor according to claim 2 , wherein the backgate comprises a p-doped structure in the first region coupled to a polysilicon-on-oxide structure in the first region, to a p-doped substrate in the first region, and to a p-doped structure in the second region.

6. The LDMOS transistor according to claim 2 , wherein a first n-doped well in the first region is coupled to a second n-doped well in the second region.

7. The LDMOS transistor according to claim 1 , wherein the source is coupled to the backgate.

8. The LDMOS transistor according to claim 1 , wherein the first region further comprises a resurf structure configured to control a charge distribution in the first region.

9. The LDMOS transistor according to claim 8 , wherein the resurf structure comprises:
a first field plate; and
a second field plate,
wherein the second field plate is positioned above the first field plate and wherein the second field plate is parallel to the first field plate, and wherein the second field plate is configured to be coupled to the first field plate.

10. An n-channel lateral double-diffused metal oxide semiconductor (LDMOS) transistor comprising:
a first region configured to operate as a junction gate field effect transistor (JFET); and
a second region configured to operate as a metal oxide semiconductor field effect transistor (MOSFET),
wherein the first region is configured to generate a first current due to weak-impact ionization, wherein the second region is configured to generate a second current due to a parasitic NPN transistor in the second region, and wherein the first region is configured to be isolated from the second region by an oxide-filled trench isolation structure such that the first current is not proportional to the second current.

Assignees

• Analog Devices International Unlimited Co

Inventors

• Coyne Edward John
• Brannick Alan
• Meskell John P

Classifications

• H01L29/0649

  Electricity · mapped topic

• H01L29/404

  Electricity · mapped topic

• H01L29/0634

  Electricity · mapped topic

• H01L29/7816 Primary

  Electricity · mapped topic

• H01L29/66681

  Electricity · mapped topic