Display device including a power supply voltage wiring having openings

US11552152B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11552152-B2
Application numberUS-201916250044-A
CountryUS
Kind codeB2
Filing dateJan 17, 2019
Priority dateJan 23, 2018
Publication dateJan 10, 2023
Grant dateJan 10, 2023

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

A display device including a lower substrate having a display region including a plurality of pixel regions, and a peripheral region surrounding the display region; a plurality of pixel structures in the plurality of pixel regions on the lower substrate; an upper substrate on the plurality of pixel structures; a seal between the lower substrate and the upper substrate in the peripheral region; and a power supply voltage wiring between the seal and the lower substrate in the peripheral region, wherein the power supply voltage wiring partially overlaps the seal, and the power supply voltage wiring includes a plurality of first openings in a portion thereof that protrudes inwardly from the seal in a first direction extending from the peripheral region into the display region.

First claim

Opening claim text (preview).

What is claimed is: 1. A display device, comprising: a lower substrate having: a display region including a plurality of pixel regions, and a peripheral region surrounding the display region; a plurality of pixel structures in the plurality of pixel regions on the lower substrate; an upper substrate on the plurality of pixel structures; a seal between the lower substrate and the upper substrate in the peripheral region; and a power supply voltage wiring between the seal and the lower substrate in the peripheral region, wherein: the power supply voltage wiring partially overlaps the seal, the power supply voltage wiring includes a plurality of first openings, the first openings are formed in a portion, which protrudes from a side wall of the seal in a first direction extending from the peripheral region into the display region, of the power supply voltage wiring, and the side wall of the seal is a boundary of the seal located most adjacent to the pixel structures. 2. The display device as claimed in claim 1 , wherein the first openings are arranged along a boundary of the display region and the peripheral region in a second direction that is perpendicular to the first direction. 3. The display device as claimed in claim 1 , wherein the power supply voltage wiring further includes a plurality of second openings in a portion thereof that overlap the seal. 4. The display device as claimed in claim 3 , wherein: the second openings are spaced apart from the first openings by a predetermined distance, the first openings and the second openings are arranged in a second direction that is perpendicular to the first direction, and the first openings and the second openings are aligned in parallel to each other. 5. The display device as claimed in claim 3 , further comprising a plurality of semiconductor elements between the lower substrate and the pixel structures, wherein each of the semiconductor elements includes: an active layer on the lower substrate; a gate electrode on the active layer; and source and drain electrodes on the gate electrode. 6. The display device as claimed in claim 5 , wherein the power supply voltage wiring and the source and drain electrodes are located at a same layer. 7. The display device as claimed in claim 5 , further comprising: a gate insulation layer on the lower substrate, the gate insulation layer covering the active layer; an insulating interlayer on the gate insulation layer, the insulating interlayer covering the gate electrode; a planarization layer on the insulating interlayer, the planarization layer covering the source and drain electrodes; and a pixel defining layer on the planarization layer. 8. The display device as claimed in claim 7 , wherein the seal is in contact with an upper surface of the planarization layer through the second openings. 9. The display device as claimed in claim 7 , wherein at least a part of the power supply voltage wiring protruding inwardly from the seal overlaps and directly contacts the planarization layer. 10. The display device as claimed in claim 3 , wherein: the power supply voltage wiring further includes a plurality of third openings spaced apart from the second openings by a predetermined distance, the third openings being arranged in a second direction that is perpendicular to the first direction, and the second openings and the third openings are aligned in parallel to each other. 11. The display device as claimed in claim 1 , further comprising a touch wiring structure along a boundary of the display region and the peripheral region on the upper substrate in the peripheral region, the touch wiring structure including a plurality of wirings. 12. The display device as claimed in claim 11 , wherein the touch wiring structure overlaps the portion of the power supply voltage wiring protruding inwardly from the seal. 13. The display device as claimed in claim 1 , wherein the plurality of pixel structures includes: a plurality of lower electrodes; a plurality of light emitting layers on the lower electrodes; and an upper electrode on the light emitting layers. 14. The display device as claimed in claim 13 , wherein: the upper electrode extends from the display region into the peripheral region, and the upper electrode located in the peripheral region is electrically connected to the power supply voltage wiring. 15. The display device as claimed in claim 14 , further comprising a first connection pattern between the upper electrode and the power supply voltage wiring, wherein the upper electrode and the power supply voltage wiring are electrically connected through the first connection pattern. 16. The display device as claimed in claim 15 , wherein: a first end of the first connection pattern is in direct contact with the upper electrode, a second end of the first connection pattern is in direct contact with the power supply voltage wiring, and the first connection pattern and the plurality of lower electrodes are located at a same layer. 17. A display device, comprising: a lower substrate having: a display region including a plurality of pixel regions, and a peripheral region surrounding the display region; a plurality of pixel structures in the plurality of pixel regions on the lower substrate; an upper substrate on the plurality of pixel structures; a seal between the lower substrate and the upper substrate in the peripheral region; a power supply voltage wiring between the seal and the lower substrate in the peripheral region, the power supply voltage wiring partially overlapping the seal, the power supply voltage wiring including a plurality of first openings in a portion thereof that are overlapped and at least partially filled with the seal, and the power supply voltage wiring having a portion that protrudes inwardly from the seal in a first direction extending from the peripheral region into the display region; a touch wiring structure along a boundary between the display region and the peripheral region in the peripheral region on the upper substrate, the touch wiring structure overlapping the portion of the power supply voltage wiring that protrudes inwardly from the seal; and a blocker surrounding the touch wiring structure in the peripheral region on a lower surface of the upper substrate, the blocker overlapping a remaining portion of the power supply voltage wiring protruded from the seal. 18. The display device as claimed in claim 17 , wherein each of the plurality of first openings directly contacts an insulating layer below the power supply voltage wiring.

Assignees

Inventors

Classifications

  • G09F9/30Primary

    in which the desired character or characters are formed by combining individual elements (panels comprising a number of electrodes in a single cell controlling light arriving from an independent light source, e.g. electro-optical or magneto-optical cell, G02F1/00) · CPC title

  • Electricity · mapped topic

  • Electricity · mapped topic

  • Electricity · mapped topic

  • Electricity · mapped topic

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US11552152B2 cover?
A display device including a lower substrate having a display region including a plurality of pixel regions, and a peripheral region surrounding the display region; a plurality of pixel structures in the plurality of pixel regions on the lower substrate; an upper substrate on the plurality of pixel structures; a seal between the lower substrate and the upper substrate in the peripheral region; …
Who is the assignee on this patent?
Samsung Display Co Ltd
What technology area does this patent fall under?
Primary CPC classification G09F9/30. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Jan 10 2023 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).