Metal-insulator-metal (MIM) capacitor and thin-film resistor (TFR) formed in an integrated circuit structure

Patent metadata

Field	Value
Publication number	US-11552011-B2
Application number	US-202117308270-A
Country	US
Kind code	B2
Filing date	May 5, 2021
Priority date	Mar 16, 2021
Publication date	Jan 10, 2023
Grant date	Jan 10, 2023

Abstract

An integrated circuit structure includes a metal-insulator-metal (MIM) capacitor and a thin-film resistor (TFR) formed concurrently, using components of shared material layers. A first metal layer may be patterned to form lower components of an interconnect structure, MIM capacitor, and TFR, and a second metal layer may be patterned to form upper components of the interconnect structure, MIM capacitor, and TFR. A via layer may be deposited to form interconnect vias, a cup-shaped bottom electrode component of the MIM capacitor, and a pair of TFR contact vias for the TFR. An insulator layer may be patterned to form both an insulator for the MIM capacitor and an insulator cap over the TFR element.

First claim

The invention claimed is:

1. An integrated circuit structure, including:
(a) a metal-insulator-metal (MIM) capacitor, comprising:
an MIM bottom electrode including:
a bottom electrode plate formed in a first metal layer; and
a bottom electrode cup including a laterally-extending bottom electrode cup base and a plurality of vertically-extending bottom electrode cup sidewalls extending upwardly from the bottom electrode cup base;

a bottom plate contact via separate from and spaced laterally apart from the bottom electrode cup;
an MIM top electrode formed in a second metal layer above the first metal layer; and
a bottom electrode connection pad conductively connected to the bottom electrode plate by the bottom plate contact via; and
an MIM insulator including:
an insulator base arranged between the MIM top electrode and the bottom electrode cup base; and
a plurality of vertically-extending insulator sidewalls, each arranged between the MIM top electrode and a respective bottom electrode cup sidewall; and

(b) a thin-film resistor (TFR), comprising:
a pair of TFR heads formed in the first metal layer; and
a TFR element connected to the pair of TFR heads by respective ones of a pair of TFR contact vias;

wherein the bottom electrode cup, the bottom plate contact via, and the pair of TFR contact vias comprise portions of a conformal metal layer.

2. The integrated circuit structure of claim 1 , wherein the MIM insulator is cup-shaped.

3. The integrated circuit structure of claim 1 , wherein respective ones of the pair of TFR contact vias and the vertically-extending bottom electrode cup sidewalls are formed in a dielectric region between the first metal layer and the second metal layer.

4. The integrated circuit structure of claim 1 , wherein:
the TFR includes a TFR insulator cap formed on the TFR element; and
the TFR insulator cap and the MIM insulator are formed in an insulator layer.

5. The integrated circuit structure of claim 1 , further comprising an interconnect structure including:
a lower interconnect wire formed in the first metal layer; and
an upper interconnect wire formed in the second metal layer and connected to the lower interconnect wire by at least one interconnect via.

6. The integrated circuit structure of claim 1 , wherein respective ones of the pair of TFR contact vias have a width in a first lateral direction and a length in a second lateral direction, the length in the second lateral direction at least 5 times the width in the first lateral direction.

7. The integrated circuit structure of claim 1 , wherein the first metal layer is an interconnect layer comprising copper or aluminum, and the second metal layer comprises aluminum.

8. The integrated circuit structure of claim 1 , wherein the first metal layer comprises a silicided polysilicon layer including a metal silicide region formed on each of a plurality of polysilicon regions.

9. An integrated circuit structure, including:
an interconnect structure comprising:
a lower interconnect wire; and
an upper interconnect wire connected to the lower interconnect wire;
at least one interconnect via connected between the lower interconnect wire and the upper interconnect wire;

a metal-insulator-metal (MIM) capacitor comprising:
a bottom electrode plate;
a bottom electrode cup formed on the bottom electrode plate;
an MIM top electrode; and
an MIM insulator arranged between the MIM top electrode and the bottom electrode cup; and

a thin-film resistor (TFR) comprising:
a pair of TFR heads; and
a TFR element connected to the pair of TFR heads;
a pair of TFR contact vias connected between the pair of TFR heads and the TFR element;

wherein the lower interconnect wire, the bottom electrode plate, and the pair of TFR heads are formed in a first metal layer;
wherein the at least one interconnect via, the bottom electrode cup, and the pair of TFR contact vias are formed from a conformal metal layer; and
wherein the upper interconnect wire and the MIM top electrode are formed in a second metal layer above the first metal layer.

10. The integrated circuit structure of claim 9 , wherein the MIM capacitor further comprises a bottom electrode connection pad formed in the second metal layer and connected to the bottom electrode plate by a bottom plate contact via.

11. The integrated circuit structure of claim 9 , wherein:
the bottom electrode cup includes:
a laterally-extending cup bottom electrode base formed on the bottom electrode plate; and
a plurality of vertically-extending bottom electrode cup sidewalls;

the MIM insulator and the MIM top electrode are at least partially located in an interior volume of the bottom electrode cup.

12. The integrated circuit structure of claim 9 , wherein the first metal layer is an interconnect layer comprising copper or aluminum, and the second metal layer comprises aluminum.

13. The integrated circuit structure of claim 9 , wherein the first metal layer comprises a silicided polysilicon layer including a metal silicide region formed on each of a plurality of polysilicon regions.

14. A method of forming an integrated circuit structure including a metal-insulator-metal (MIM) capacitor and a thin-film resistor (TFR), the method comprising:
forming a plurality of first conductive elements in a first metal layer, the plurality of first conductive elements including:
an MIM bottom electrode plate; and
first and second TFR heads;

forming a MIM bottom electrode cup over the MIM bottom electrode plate;
forming a first TFR contact via conductively connected to the first TFR head and a second TFR contact via conductively connected to the second TFR head;
wherein the MIM bottom electrode cup, the first TFR contact via, and the second TFR contact via are formed concurrently;
forming a TFR element conductively connected to the first TFR head through the first TFR contact via and conductively connected to the second TFR head through the second TFR contact via;
forming an insulator layer above the first metal layer to define:
a cup-shaped MIM insulator over the MIM bottom electrode cup; and
a TFR insulator cap over the TFR element; and

forming a plurality of second conductive elements in a second metal layer above the first metal layer, the plurality of second conductive elements including an MIM top electrode over the cup-shaped MIM insulator;
wherein the MIM insulator is formed between the MIM bottom electrode plate and the MIM top electrode.

15. The method of claim 14 , wherein the MIM bottom electrode cup includes a bottom electrode cup base and multiple vertically-extending bottom electrode cup sidewalls extending upwardly from the bottom electrode cup base; and
wherein the MIM insulator includes multiple vertically-extending insulator sidewalls, each formed adjacent a respective vertically-extending MIM bottom electrode sidewall.

16. The method of claim 14 , further comprising, after forming the plurality of first conductive elements in the first metal layer and before forming the TFR element,
forming at least one MIM bottom plate contact via concurrently with the MIM bottom electrode cup, the first TFR contact via, and the second TFR contact via; and
wherein the plurality of second conductive elements includes a bottom electrode connection pad connected to the MIM bottom electrode plate by at least one MIM bottom plate contact via.

17. The method of claim 14 , wherein the MIM bottom electrode cup includes:
a laterally-extending bottom electrode cup base; and
multiple vertically-extending bottom electrode cup s

Assignees

• Microchip Tech Inc

Inventors

• Leng Yaojian

Classifications

• H10W20/498

  Resistive arrangements or effects of, or between, wiring layers · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W20/496 Primary

  Capacitor integral with wiring layers · CPC title

• H01L23/5223 Primary

  Electricity · mapped topic