Integrated circuits and methods for dynamic allocation of one-time programmable memory

Patent metadata

Field	Value
Publication number	US-11551769-B2
Application number	US-201816002195-A
Country	US
Kind code	B2
Filing date	Jun 7, 2018
Priority date	Aug 31, 2016
Publication date	Jan 10, 2023
Grant date	Jan 10, 2023

Abstract

A one-time programmable (OTP) memory has a plurality of pages. A predefined section of each page is configured to store error policy bits. When an indicator in a first predefined location has a first value, the page is configured to store data with error correction code (ECC) bits, and when the indicator has a second value, at least a portion of the page is configured to store data with redundancy. Address translation circuitry is configured to, in response to receiving an access address, use a second predefined location of an accessed page of the plurality of pages accessed by the access address to determine a physical address in the accessed page which corresponds to the access address.

First claim

What is claimed is:

1. An integrated circuit, the integrated circuit comprising:
a one-time programmable (OTP) memory having a plurality of pages, wherein a predefined section of each page is configured to store error policy bits, wherein when an indicator in a first predefined location of the predefined section has a first value, the page is configured to store data with error correction code (ECC) bits, and when the indicator has a second value, at least a portion of the page is configured to store data with redundancy; and
address translation circuitry configured to, in response to receiving an access address, use a second predefined location of an accessed page of the plurality of pages accessed by the access address to determine a physical address in the accessed page which corresponds to the access address.

2. The integrated circuit of claim 1 , wherein when the indicator of the accessed page has the first value, the physical address corresponding to the access address has a first physical address value, and when the indicator of the accessed page has the second value, the physical address corresponding to the access address has a second physical address value different from the first physical address value.

3. The integrated circuit of claim 2 , wherein the second physical address has a greater offset from a base address of the accessed page as compared to the first physical address.

4. The integrated circuit of claim 1 , further comprising output circuitry configured to, when the indicator of the accessed page has the first value, provide data from the physical address as output data.

5. The integrated circuit of claim 4 , wherein the output circuitry is configured to, when the indicator of the accessed page has the second value, provide data from the physical address aggregated with data from a second physical address of the accessed page as output data.

6. The integrated circuit of claim 5 , wherein the second physical address is in an adjacent line of the accessed page to the physical address.

7. The integrated circuit of claim 5 , wherein the OTP memory further comprises:
ECC and redundancy logic configured to provide an error indicator for the output data, wherein the ECC and redundancy logic is configured to, when the indicator has the first value, use corresponding ECC bits to provide the error indicator and when the indicator of the accessed page has the second value, use corresponding redundant data to provide the error indicator.

8. The integrated circuit of claim 1 , wherein for each page, when the indicator has the second value, a remaining portion of the page is configured to store data with ECC bits.

9. The integrated circuit of claim 1 , wherein the OTP memory has a master word configured to store attribute information for the OTP memory.

10. The integrated circuit of claim 9 , wherein the attribute information comprises a page size for the OTP memory.

11. The integrated circuit of claim 9 , wherein the attribute information comprises lock bits for each page of the plurality of pages of the OTP memory.

12. The integrated circuit of claim 9 , further comprising:
a page offset calculator configured to use the page size of the attribute information and the access address to determine a page base address of the accessed page.

13. A method of operating a one-time programmable (OTP) memory device having a plurality of pages, wherein a predefined section of each page is configured to store error policy bits, the method comprising:
when an indicator in a first predefined location of a page has a first value, storing data with error correction code (ECC) bits in the page, and when the indicator has a second value, storing data with redundancy in the page; and
in response to receiving an access address, using a second predefined location of an accessed page of the plurality of pages accessed by the access address to determine a physical address in the accessed page which corresponds to the access address.

14. The method of claim 13 , wherein when the indicator of the accessed page has the first value, the physical address corresponding to the access address has a first physical address value, and when the indicator of the accessed page has the second value, the physical address corresponding to the access address has a second physical address value different from the first physical address value.

15. The method of claim 14 , wherein the second physical address has a greater offset from a base address of the accessed page as compared to the first physical address.

16. The method of claim 13 , further comprising, when the indicator of the accessed page has the first value, providing data from the physical address as output data.

17. The method of claim 16 , further comprising, when the indicator of the accessed page has the second value, providing data from the physical address aggregated with data from a second physical address of the accessed page as output data.

18. The method of claim 17 , wherein the second physical address is in an adjacent line of the accessed page to the physical address.

19. The method of claim 17 , further comprising:
providing an error indicator for the output data, wherein the ECC and redundancy logic is configured to, when the indicator has the first value, using corresponding ECC bits to provide the error indicator and when the indicator of the accessed page has the second value, using corresponding redundant data to provide the error indicator.

20. The method of claim 13 , further comprising, when the indicator has the second value, storing data with ECC bits in a remaining portion of the page.

Assignees

• Nxp Usa Inc

Inventors

• Pandey Rakesh
• Arora Mohit
• Xie Jun

Classifications

• G11C17/16 Primary

  using electrically-fusible links · CPC title

• G06F11/1068

  in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence) · CPC title

• G06F2212/2142

  using write-once memory, e.g. OTPROM · CPC title

• G06F12/10

  Address translation · CPC title

• G11C29/52

  Protection of memory contents; Detection of errors in memory contents · CPC title