Apparatuses and methods including memory commands for semiconductor memories

Patent metadata

Field	Value
Publication number	US-11550741-B2
Application number	US-202117167475-A
Country	US
Kind code	B2
Filing date	Feb 4, 2021
Priority date	Nov 29, 2017
Publication date	Jan 10, 2023
Grant date	Jan 10, 2023

Abstract

Apparatuses and methods including memory commands for semiconductor memories are described. A controller provides a memory system with memory commands to access memory. The commands are decoded to provide internal signals and commands for performing operations, such as operations to access the memory array. The memory commands provided for accessing memory may include timing command and access commands. Examples of access commands include a read command and a write command. Timing commands may be used to control the timing of various operations, for example, for a corresponding access command. The timing commands may include opcodes that set various modes of operation during an associated access operation for an access command.

First claim

What is claimed is:

1. A method, comprising:
providing a timing command to a memory, the timing command configured to enable a clock signal synchronization option and to set a delay for when the memory performs a clock signal synchronization operation following the timing command when the clock signal synchronization option is enabled;
providing an access command to the memory, wherein the access command is associated with the timing command; and
providing a data clock signal to the memory to be synchronized by the memory at a time based on the delay set by the timing command.

2. The method of claim 1 , further comprising providing a second access command associated with the timing command, wherein the second access command is directed to a second memory.

3. The method of claim 2 , further comprising providing a third access command associated with the timing command, wherein the third access command is directed to the memory.

4. The method of claim 1 wherein providing the data clock signal to the memory comprises providing the data clock signal having a static level for a first time and providing the data clock signal having changing clock levels thereafter.

5. The method of claim 1 , further comprising providing a clock signal for timing receipt of the timing command and the access command.

6. The method of claim 1 wherein the timing command comprises:
a first part including a clock signal synchronization option field for a value to enable the clock signal synchronization option; and
a second part including an opcode field for a value to set the delay for when the memory performs a clock signal synchronization operation.

7. A method, comprising:
receiving a timing command configured to enable a clock signal synchronization option and to set a delay for when a clock signal synchronization operation is performed following the timing command when the clock signal synchronization option is enabled;
receiving an access command associated with the timing command; and
synchronizing a data clock signal and internal clock signals generated therefrom at a time based on the delay set by the timing command.

8. The method of claim 7 wherein the timing command is further configured to set a time for maintaining the input buffer as activated.

9. The method of claim 8 , further comprising:
activating an input buffer configured to receive the data clock signal;
receiving the data clock signal at the input buffer; and
maintaining the input buffer as activated following completion of an access operation for the access command.

10. The method of claim 7 wherein the access command comprises a write command, and the method further comprises receiving data associated with the write command at a time defined by a write latency following the access command.

11. The method of claim 7 wherein the access command comprises a read command, and the method further comprises providing data associated with the read command at a time defined by a read latency following the access command.

12. The method of claim 11 , further comprising providing a dock signal with the data wherein the clock signal is based on the data clock signal.

13. The method of claim 7 wherein synchronizing the data clock signal comprises determining a phase relationship between the data clock signal and the internal clock signals.

14. The method of claim 7 wherein the clock signal synchronization operation comprises a fast clock signal synchronization operation with the data clock signal.

15. A method comprising:
providing a timing command to a first memory and a second memory, the timing command configured to enable a clock signal synchronization option and to set a delay for when the first memory and second memory perform a clock signal synchronization operation following the timing command when the clock signal synchronization option is enabled;
providing a first access command to the first memory, wherein the first access command is associated with the timing command; and
providing a data dock signal to the first memory and the second memory to be synchronized by the first memory and the second memory at a time based on the delay set by the timing command.

16. The method of claim 15 , further comprising activating a first select signal associated with the first memory and a second select signal associated with the second memory simultaneously before or when the timing command is provided.

17. The method of claim 15 , wherein a first select signal associated with the first memory is active and a second select signal associated with the second memory is inactive when the first access command is provided.

18. The method of claim 15 , further comprising providing a second access command to the second memory after the first access command, wherein the second access command is associated with the timing command.

19. The method of claim 18 , wherein a first select signal associated with the first memory is in active and a second select signal associated with the second memory is active when the second access command is provided.

Assignees

• Micron Technology Inc

Inventors

• Kim Kang-Yong
• Gans Dean

Classifications

• G11C7/222

  Clock generating, synchronizing or distributing circuits within memory device · CPC title

• G11C16/08

  Address circuits; Decoders; Word-line control circuits · CPC title

• G11C29/023

  in clock generator or timing circuitry · CPC title

• G06F13/1689 Primary

  Synchronisation and timing concerns (synchronisation on a memory bus G06F13/4234) · CPC title

• G06F9/30145

  Instruction analysis, e.g. decoding, instruction word fields · CPC title