Packet backpressure detection method, apparatus, and device

US11550694B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11550694-B2
Application numberUS-201916653326-A
CountryUS
Kind codeB2
Filing dateOct 15, 2019
Priority dateSep 30, 2016
Publication dateJan 10, 2023
Grant dateJan 10, 2023

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

A packet backpressure detection method and apparatus are provided. The method includes: a device which having a Peripheral Component Interconnect Express (PCIe) port storing a plurality of packets for transmission in a packet queue and storing a packet that is to be transmitted next in a first buffer, where the queue comprises a plurality of packets that are to be transmitted via the PCIe port; and the queue is stored in a second buffer; recording a storage duration of each packet stored in the first buffer, and accumulating the storage duration of each packet stored in the first buffer; removing the packet from the first buffer after the packet is transmitted via the PCIe port; and generating an indication of packet pressure at the PCIe port based on the accumulated storage duration.

First claim

Opening claim text (preview).

What is claimed is: 1. A packet backpressure detection method by a device having a Peripheral Component Interconnect Express (PCIe) port, comprising: storing a plurality of packets that are to be transmitted, via the PCIe port in a packet queue in a first buffer; moving a packet that is to be transmitted next from the first buffer to a second buffer; recording a storage duration of each packet stored in the second buffer; accumulating the storage duration of each packet stored in the second buffer as an accumulated storage duration; generating an indication of packet pressure at the PCIe port when the accumulated storage duration reaches a first value; and resetting the accumulated storage duration to 0 in a preset condition. 2. The method according to claim 1 , wherein the second buffer stores a maximum of one packet at any moment. 3. The method according to claim 1 , wherein the second buffer stores at least two packets at any moment, the first buffer is smaller in size than the second buffer. 4. The method according to claim 1 , wherein the resetting the accumulated storage duration to 0 in a preset condition, comprises: resetting a timer; starting the timer to record time; resetting the accumulated storage duration to 0 when a time recorded by the timer reaches a second value. 5. The method according to claim 1 , wherein the resetting the accumulated storage duration to 0 in a preset condition, comprises: recording a quantity of packets that have been stored in the second buffer, and when the quantity reaches a third value, resetting the accumulated storage duration to 0. 6. The method according to claim 1 , wherein the storage duration that is of each packet and is successively recorded by the device forms a duration queue, and the method further comprises: when a length of the duration queue reaches a fourth value, deleting the earliest-recorded storage duration from the duration queue; and subtracting, from the accumulated storage duration, the earliest-recorded storage duration that is deleted from the duration queue. 7. The method according to claim 1 , wherein the storing a packet that is to be transmitted next in a second buffer, comprising: when each packet in a packet queue in a first direction of the PCIe port becomes a packet that is to be transmitted next in the second buffer at the PCIe port, moving, in the second buffer, the packet that needs to be sent in the first direction, wherein the first direction is an upstream direction or a downstream direction of the PCIe port. 8. The method according to claim 1 , the method further comprises: when each packet in a packet queue in a second direction of the PCIe port becomes a packet that is to be transmitted next in the second buffer at the PCIe port, moving, in a third buffer, the packet that needs to be sent in the second direction, wherein the second direction is opposite to the first direction, the packet stored in the third buffer is removed from the third buffer after being sent by using the PCIe port, and the third buffer stores a maximum of one packet at any moment; recording storage duration of each packet stored in the third buffer, and accumulating the recorded storage duration of each packet stored in the third buffer; removing the packet from the third buffer after the packet is transmitted via the PCIe port; and when the second accumulated duration reaches the sixth value, generating a second indication of packet pressure at the PCIe port based on the second accumulated storage duration. 9. The method according to claim 1 , wherein the method further comprises: removing the packet from the second buffer after the packet is transmitted via the PCIe port. 10. A packet backpressure detection device, comprising: a processor; a memory; a PCIe port; wherein the memory includes a plurality of instructions stored thereon, that when executed by the processor, causes the device to: store a plurality of packets that are to be transmitted to a PCIe port in another device via the PCIe port in a packet queue in a first buffer; moving a packet that is to be transmitted next from the first buffer to a second buffer; record a storage duration of each packet stored in the second buffer; accumulate the storage duration of each packet stored in the second buffer as an accumulated storage duration; generate an indication of packet pressure at the PCIe port when the accumulated storage duration reaches the first value; and resetting the accumulated storage duration to 0 in a preset condition. 11. The packet backpressure detection device according to claim 10 , wherein the second buffer stores a maximum of one packet at any moment. 12. The packet backpressure detection device according to claim 10 , wherein the second buffer stores at least two packets at any moment, the first buffer is smaller in size than the second buffer. 13. The packet backpressure detection device according to claim 10 , wherein when executed by the processor, cause the device to: reset timer to record time; and reset the accumulated storage duration to 0 when a time recorder by the timer reaches a second value. 14. The packet backpressure detection device according to claim 13 , wherein when executed by the processor, cause the device to: record a quantity of packets that have been stored in the second buffer; and when the quantity reaches a third value, reset the accumulated storage duration to 0. 15. The packet backpressure detection device according to claim 13 , wherein when executed by the processor, cause the processor to: when a length of the duration queue reaches a fourth value, delete the earliest-recorded storage duration from the duration queue; and subtract from the accumulated storage duration, the earliest-recorded storage duration that is deleted from the duration queue. 16. The packet backpressure detection device according to claim 10 , wherein when executed by the processor, cause the processor to: when each packet in a packet queue in a first direction of the PCIe port becomes a packet that is to be transmitted next in the second buffer at the PCIe port, moving, in the second buffer, the packet that needs to be sent in the first direction, wherein the first direction is an upstream direction or a downstream direction of the PCIe port; and when each packet in a packet queue in a second direction of the PCIe port becomes a packet that is to be transmitted next in the second buffer at the PCIe port, move, in a third buffer, the packet that needs to be sent in the second direction, wherein the second direction is opposite to the first direction, the packet stored in the third buffer is removed from the third buffer after being sent by using the PCIe port, and the third buffer stores a maximum of one packet at any moment; record storage duration of each packet stored in the third buffer; accumulate the recorded storage duration of each packet stored in the third buffer; remove the packet from the third buffer after the packet is transmitted via the PCIe port; and when the second accumulated duration reaches the sixth value, generate a second indication of packet pressure at the PCIe port based on the second accumulated storage duration. 17. A non-transitory computer-readable storage medium comprising instructions which, when executed by a processor in device the device to: store a plurality of packets that are to be transmitted to a PCIe port in another device via the PCIe port in a packet queue in a first buffer; move a packet that is to be transmitted next from the first

Assignees

Inventors

Classifications

  • using a handshaking protocol, e.g. Centronics connection · CPC title

  • where the computing system component is an input/output interface (interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units G06F13/00) · CPC title

  • PCI express · CPC title

  • for access to input/output bus · CPC title

  • on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US11550694B2 cover?
A packet backpressure detection method and apparatus are provided. The method includes: a device which having a Peripheral Component Interconnect Express (PCIe) port storing a plurality of packets for transmission in a packet queue and storing a packet that is to be transmitted next in a first buffer, where the queue comprises a plurality of packets that are to be transmitted via the PCIe port;…
Who is the assignee on this patent?
Huawei Tech Co Ltd
What technology area does this patent fall under?
Primary CPC classification G06F11/3485. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Jan 10 2023 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 10 related publications on this page (citations in our corpus or others sharing the same primary CPC).