Unified hypercall interface across processors in virtualized computing systems

Patent metadata

Field	Value
Publication number	US-11550609-B2
Application number	US-202016744356-A
Country	US
Kind code	B2
Filing date	Jan 16, 2020
Priority date	Jan 16, 2020
Publication date	Jan 10, 2023
Grant date	Jan 10, 2023

Abstract

An example method of interfacing with a hypervisor in a computing system is described, which includes a processor having at least three hierarchical privilege levels including a third privilege level more privileged than a second privilege level, the second privilege level more privileged than a first privilege level. The method includes: identifying an input/output (I/O) space instruction, not supported by the processor, to be performed for backdoor communication between the hypervisor and guest software executing in a virtual machine (VM) managed by the hypervisor, the hypervisor executing at the third privilege level; writing one or more parameters to one or more registers of the processor that are mapped to one or more unsupported registers used by the I/O space instruction; writing a value indicative of the I/O space instruction to a designated register of the processor; executing an instruction, by the guest software executing at the first or second privilege level, which is trapped to the third privilege level.

First claim

We claim:

1. A method of interfacing with a hypervisor in a computing system, which includes a processor having at least three hierarchical privilege levels associated with respective distinct code execution privileges, the hierarchical privilege levels including: a third privilege level accessible by code executing at the third privilege level, a second privilege level accessible by code executing at the third privilege level and the second privilege level, and a first privilege level accessible by code executing at any of the first privilege level, the second privilege level, or the third privilege level, wherein the third privilege level is higher than the second privilege level and the second privilege level is higher than the first privilege level, the method comprising:
identifying, by a guest support tool executing in a virtual machine (VM) managed by the hypervisor, an input/output (I/O) space instruction, not supported by the processor, to be performed for backdoor communication between the hypervisor and the guest support tool executing in the VM managed by the hypervisor, the hypervisor executing at the third privilege level, wherein the processor comprises a plurality of registers comprising:
at least one first register accessible by code executing at the first privilege level or higher, at least one second register accessible by code executing at the second privilege level or higher and at least one third register accessible by code executing at the third privilege level or higher; and

writing, by the guest support tool, one or more parameters to one or more registers of the processor that are mapped to one or more unsupported registers used by the I/O space instruction, wherein the one or more parameters comprise one or more of:
an I/O port address;
a virtual address of a memory of the computing system; or
a number of repetitions to perform the I/O space instruction;

writing a value indicative of the I/O space instruction to a designated register of the processor; and
executing an instruction, by the guest support tool executing at the first or second privilege level, which is trapped to the third privilege level, wherein executing the instruction enables the hypervisor to:
identify the I/O space instruction based on the value stored in the designated register;
obtain parameters associated with the I/O space instruction from the one or more registers; and
emulate the I/O space instruction in accordance with the identified I/O space instruction and the one or more parameters.

2. The method of claim 1 , further comprising:
trapping, at the hypervisor, the instruction executed by the guest software;
reading the value from the designated register to identify the I/O space instruction to perform; and
reading the one or more parameters from the one or more registers of the processor to obtain the parameters of the I/O space instruction to perform.

3. The method of claim 1 , wherein the I/O space instruction is one of: an instruction to read from a port or an instruction to write to a port.

4. The method of claim 1 , wherein the I/O space instruction is one of: an instruction to write to a port or an instruction to repeatedly write to a port.

5. The method of claim 1 , wherein the one or more parameters comprise an I/O port address and an output value.

6. The method of claim 1 , wherein the value indicative of the I/O space instruction includes a portion indicative of transfer size, a portion indicative of transfer direction, and a portion indicative of instruction type.

7. A non-transitory computer readable medium having instructions stored thereon that when executed by a processor cause the processor to perform a method of interfacing with a hypervisor in a computing system, which includes the processor having at least three hierarchical privilege levels associated with respective distinct code execution privileges, the hierarchical privilege levels including a third privilege level accessible by code executing at the third privilege level, a second privilege level accessible by code executing at the third privilege level and the second privilege level, and a first privilege level accessible by code executing at any of the first privilege level, the second privilege level, or the third privilege level, wherein the third privilege level is higher than the second privilege level and the second privilege level is higher than the first privilege level, the method comprising:
identifying, by a guest support tool executing in a virtual machine (VM) managed by the hypervisor, an input/output (I/O) space instruction, not supported by the processor, to be performed for backdoor communication between the hypervisor and the guest support tool executing in the VM managed by the hypervisor, the hypervisor executing at the third privilege level, wherein the processor comprises a plurality of registers comprising:
at least one first register accessible by code executing at the first privilege level or higher, at least one second register accessible by code executing at the second privilege level or higher, and at least one third register accessible by code executing at the third privilege level or higher;

writing, by the guest support tool, one or more parameters to one or more registers of the processor that are mapped to one or more unsupported registers used by the I/O space instruction, wherein the one or more parameters comprise one or more of:
an I/O port address;
a virtual address of a memory of the computing system; or
a number of repetitions to perform the I/O space instruction;

writing a value indicative of the I/O space instruction to a designated register of the processor; and
executing an instruction, by the guest support tool executing at the first or second privilege level, which is trapped to the third privilege level, wherein executing the instruction enables the hypervisor to:
identify the I/O space instruction based on the value stored in the designated register;
obtain parameters associated with the I/O space instruction from the one or more registers; and
emulate the I/O space instruction in accordance with the identified I/O space instruction and the one or more parameters.

8. The non-transitory computer readable medium of claim 7 , wherein the method further comprises:
trapping, at the hypervisor, the instruction executed by the guest software;
reading the value from the designated register to identify the I/O space instruction to perform; and
reading the one or more parameters from the one or more registers of the processor to obtain the parameters of the I/O space instruction to perform.

9. The non-transitory computer readable medium of claim 7 , wherein the I/O space instruction is one of: an instruction to read from a port or an instruction to write to a port.

10. The non-transitory computer readable medium of claim 7 , wherein the I/O space instruction is one of: an instruction to write to a port or an instruction to repeatedly write to a port.

11. The non-transitory computer readable medium of claim 7 , wherein the one or more parameters comprise an I/O port address and an output value.

12. The non-transitory computer readable medium of claim 7 , wherein the value indicative of the I/O space instruction includes a portion indicative of transfer size, a portion indicative of transfer direction, and a portion indicative of instruction type.

13. A computing system, comprising:
a hardware platform having a processor and a memory, the processor having at least three hierarchical privilege levels associated with respective distinct code execution privileges, the hierarchical privilege levels including a thi

Assignees

• Vmware Inc

Inventors

• Warkentin Andrei
• Laplace Cyprien
• Duchesne Regis
• Fainkichen Alexander
• Hiriyuru Shruthi Muralidhara
• Li Ye

Classifications

• G06F2009/45579

  I/O management, e.g. providing access to device drivers or storage · CPC title

• G06F9/45533 Primary

  Hypervisors; Virtual machine monitors · CPC title

• G06F9/45558 Primary

  Hypervisor-specific management and integration aspects · CPC title