Capacitive micro structure

Patent metadata

Field	Value
Publication number	US-11548779-B2
Application number	US-201816624181-A
Country	US
Kind code	B2
Filing date	Jun 15, 2018
Priority date	Jun 19, 2017
Publication date	Jan 10, 2023
Grant date	Jan 10, 2023

Abstract

A micro structure with a substrate having a top surface; a first electrode with a horizontal orientation parallel to the top surface of the substrate, wherein the first electrode is embedded within the substrate so that a top surface of the first electrode coincides with the top surface of the substrate; a dielectric layer arranged on the top surface of the first electrode; and a second electrode arranged above the dielectric layer.

First claim

The invention claimed is:

1. A micro structure comprising:
a silicon substrate having a top surface; and
a metal-insulator-metal (MIM) capacitor comprising:
a first electrode with a horizontal orientation parallel to the top surface of the silicon substrate, wherein the first electrode is embedded within the silicon substrate so that a top surface of the first electrode coincides with the top surface of the substrate;
a dielectric layer arranged on the top surface of the first electrode; and
a second electrode arranged above the dielectric layer,

the micro structure further comprising:
a first connecting element arranged on the silicon substrate and configured to provide a conductive connection to a first horizontal end of the top surface of the first electrode; and
a passivation layer formed on the silicon substrate between the silicon substrate and the first connecting element.

2. The micro structure of claim 1 , wherein the top surface of the first electrode is polished.

3. The micro structure of claim 1 , wherein thickness of the first electrode is more than 5 μm.

4. The micro structure of claim 1 , wherein
the second electrode is arranged directly on a top surface of the dielectric layer.

5. The micro structure of claim 4 , wherein
a first horizontal end of the top surface of the first electrode is left uncovered by the dielectric layer and the dielectric layer extends over a second horizontal end of the top surface of the first electrode.

6. The micro structure of claim 5 , wherein
a first horizontal end of the top surface of the dielectric layer is left uncovered by the second electrode and the second electrode extends to a second horizontal end of the top surface of the dielectric layer.

7. A semiconductor apparatus comprising the micro structure of claim 1 .

8. The semiconductor apparatus of claim 7 , further comprising an integrated passive device (IPD).

9. The semiconductor apparatus of claim 7 , further comprising at least one barrier layer extending on a surface of a metal layer of the first electrode.

10. The semiconductor apparatus of claim 7 , wherein the dielectric layer comprises an Atomic Layer Deposition (ALD) grown aluminum oxide layer or a plasma enhanced chemical vapor deposition (PECVD) layer.

11. The micro structure of claim 6 , further comprising:
a second connecting element arranged on the silicon substrate and configured to provide connection to a second horizontal end of the second electrode adjacent to the second horizontal end of the top surface of the of the dielectric layer.

12. The micro structure of claim 1 , wherein the first connecting element comprises a metal layer pad.

13. The micro structure of claim 1 , wherein the dielectric layer is made of SiO2, Ta2O5, HfO, or ZrO2.

14. The micro structure of claim 1 , wherein the first electrode comprises thick metallization of >1 μm.

15. A method of forming a micro structure comprising a metal-insulator-metal (MIM) capacitor, the method comprising:
providing a silicon substrate having a top surface;
forming the MIM capacitor by:
forming a first electrode with a horizontal orientation parallel to the top surface of the silicon substrate, wherein the first electrode is embedded within the silicon substrate so that a top surface of the first electrode coincides with the top surface of the silicon substrate;
forming a dielectric layer on the top surface of the first electrode; and
forming a second electrode above the dielectric layer; the method further comprising:

forming a first connecting element on the silicon substrate, the first connecting element configured to provide a conductive connection to a first horizontal end of the top surface of the first electrode; and
forming a passivation layer on the silicon substrate between the silicon substrate and the first connecting element.

Assignees

• Teknologian Tutkimuskeskus Vtt Oy

Inventors

• Kattelus Hannu
• Vähä-Heikkilä Tauno

Classifications

• B81B2201/016

  having a bridge fixed on two ends and connected to one or more dimples · CPC title

• B81C2203/0714

  Forming the micromechanical structure with a CMOS process · CPC title

• B81B2201/0221

  Variable capacitors · CPC title

• B81C1/00246 Primary

  Monolithic integration, i.e. micromechanical structure and electronic processing unit are integrated on the same substrate · CPC title

• B81B3/0086 Primary

  Electrical characteristics, e.g. reducing driving voltage, improving resistance to peak voltage · CPC title