Modular motherboard for a computer system and method thereof

Patent metadata

Field	Value
Publication number	US-11546992-B2
Application number	US-201816057580-A
Country	US
Kind code	B2
Filing date	Aug 7, 2018
Priority date	Aug 7, 2017
Publication date	Jan 3, 2023
Grant date	Jan 3, 2023

Abstract

One feature pertains to a modular design of a motherboard for a computer system. The mother board is disaggregated into a CPU board and an IO board. The CPU board contains at least one CPU, the associated memory subsystem and the voltage regulator module. The integrated IO ports escape to a high speed connector mating with its counterpart on an IO board which contains all peripheral devices including system logic not part of the CPU. In a multi-socket configuration the CPUs are on the CPU board and the processor interconnects are routed directly in a point to point manner.

First claim

What is claimed is:

1. A modular computer motherboard, comprising:
a first printed circuit board assembly, the first printed circuit board assembly comprising:
a first printed circuit board having a first surface and an opposite second surface;
a first central processing unit mounted on the first surface of the first printed circuit board, the first central processing unit having integrated input/output ports;
a system memory socket mounted on the first surface of the first printed circuit board;
a power supply for powering the central processing unit and the memory slot; and
a first high speed data connector mounted on the second surface of the first printed circuit board and connected to the integrated input/output ports of the first central processing unit on the first surface of the printed circuit board; and

a second printed circuit board assembly mounted to the second surface of the first printed circuit board, the second printed circuit board assembly comprising:
a second printed circuit board having a first surface and an opposite second surface;
an input/output interface, coupled to the first surface of the second printed circuit board, for providing input/output functionality; and
a second high speed data connector mounted on the second surface of the second printed circuit board and adapted to couple with the first high speed data connector mounted on the second surface of the first printed circuit board and a high speed peripheral device interface; and

wherein the input/output functionality of the combined first and second circuit boards is determined by the functionality of the second printed circuit board;
wherein the first high speed data connector interfaces to the second printed circuit board for providing input/output functionality; and
wherein the second high speed data connector interfaces to the first printed circuit board for providing central processing functionality.

2. The motherboard of claim 1 , wherein the second printed circuit board assembly further includes at least one of a system logic integrated circuit, a management controller and a high speed peripheral device interface mounted thereon.

3. The motherboard of claim 1 , further comprising:
a boot device removably coupled to the second printed circuit board assembly.

4. The motherboard of claim 1 , wherein the first printed circuit board assembly further comprises:
a second central processing unit mounted on the first surface of the first printed circuit board;
an interconnect bus, between the first central processing unit and the second central processing unit, routed point to point on the first printed circuit board; and
wherein signals from the integrated input/output ports from the first and second central processing units share the first high speed data connector.

5. The motherboard of claim 4 , further comprising:
a third high speed connector mounted on the first printed circuit board assembly and configured to couple with a fourth high speed connector mounted on the second printed circuit board assembly.

6. The motherboard of claim 5 , wherein the first high speed data connector is positioned adjacent to the first central processing unit and away from the second processing unit; and wherein the third high speed connector is positioned adjacent to the second central processing unit and away from the first central processing unit.

7. The motherboard of claim 6 , wherein the first high speed data connector is coupled to only the first central processing unit, and the third high speed connector is coupled to only the second central processing unit.

8. The motherboard of claim 4 , wherein the first high speed data connector is positioned between the first and second central processing units.

9. The motherboard of claim 4 , wherein the first high speed data connector carries signals between the first and second central processing units and the second printed circuit board assembly.

10. A method for manufacturing a computer motherboard with reduced length interconnection traces, comprising:
dividing the motherboard into a first printed circuit board assembly and a second printed circuit board assembly;
forming a first printed circuit board assembly, the first printed circuit board comprising:
a first printed circuit board having a first surface and an opposite second surface;
a first central processing unit mounted on the first surface of the first printed circuit board, the first central processing unit having integrated input/output ports;
a system memory socket mounted on the first surface of the first printed circuit board;
a power supply to provide power to the central processing unit and the memory slot; and
a first high speed data connector mounted on the second surface of the first printed circuit board and connected to the integrated input/output ports of the first central processing unit on the first surface of the printed circuit board; and

forming a second printed circuit board assembly mounted to the second surface of the first printed circuit board, the second printed circuit board comprising:
a second printed circuit board with a first surface and an opposite second surface;
an input/output interface, coupled to the first surface of the second printed circuit board, for providing input/output functionality;
a high-speed peripheral device interface; and
a second high speed data connector mounted on the second surface of the second printed circuit board, and adapted to couple with the first high speed data connector mounted on the second surface of the first printed circuit board and a high speed peripheral device interface; and

wherein the input/output functionality of the combined first and second circuit boards is determined by the functionality of the second printed circuit board;
wherein the first high speed data connector interfaces to the second printed circuit board for providing input/output functionality; and
wherein the second high speed data connector interfaces to the first printed circuit board for providing central processing functionality.

11. The method of claim 10 , wherein the second printed circuit board assembly includes at least one of a system logic integrated circuit and a management controller integrated thereon.

12. The method of claim 10 , wherein a boot device is removably attached to the second printed circuit board assembly.

13. The method of claim 10 , wherein the first printed circuit board assembly further comprises:
a second central processing unit mounted on the first surface of the first printed circuit board;
an interconnect bus, between the first central processing unit and the second central processing unit, routed point to point on the first printed circuit board; and
wherein signals from the integrated input/output ports from the first and second central processing units share the same first high speed data connector.

14. The method of claim 10 , wherein the first printed circuit board assembly further comprises:
a second central processing unit integrated on the first printed circuit board assembly; and,
wherein an interconnect bus, between the first and the second central processing unit, routed point to point on the printed circuit board;
wherein signals from the integrated input/output ports of the first central processing unit are routed to the first connector; and
wherein signals from the integrated input/output ports of the second central processing unit are routed to a third connector configured to mate with a fourth connector on the second printed circuit board assembly.

15. A computer motherboard, comprising:
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Assignees

• Sanmina Corp

Inventors

• Hill Charles C
• Schuette Franz Michael

Classifications

• H05K2201/10159

  Memory · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

• G06F13/409 Primary

  Mechanical coupling (back panels H05K7/1438) · CPC title

• H05K2201/042

  Stacked spaced PCBs; Planar parts of folded flexible circuits having mounted components in between or spaced from each other · CPC title

• H05K2201/10189

  Non-printed connector · CPC title