Low-noise, high-accuracy single-ended input stage for continuous-time sigma delta (CTSD) analog-to-digital converter (ADC)

Patent metadata

Field	Value
Publication number	US-11545996-B1
Application number	US-202117410163-A
Country	US
Kind code	B1
Filing date	Aug 24, 2021
Priority date	Aug 24, 2021
Publication date	Jan 3, 2023
Grant date	Jan 3, 2023

Abstract

Systems, devices, and methods related to low-noise, high-accuracy single-ended continuous-time sigma-delta (CTSD) analog-to-digital converter (ADC) are provided. An example single-ended CTSD ADC includes a pair of input nodes to receive a single-ended input signal and input circuitry. The input circuitry includes a pair of switches, each coupled to one of the pair of input nodes; and an amplifier to provide a common mode signal at a pair of first nodes, each before one of the pair of switches. The single-ended CTSD ADC further includes digital-to-analog converter (DAC) circuitry; and integrator circuitry coupled to the input circuitry and the DAC circuitry via a pair of second nodes.

First claim

The invention claimed is:

1. A single-ended continuous time sigma delta (CTSD) analog-to-digital converter (ADC) comprising:
a pair of input nodes to receive a single-ended input signal;
input circuitry comprising:
a pair of switches, each coupled to one of the pair of input nodes; and
an amplifier to provide a common mode signal at a pair of first nodes, each before one of the pair of switches;

digital-to-analog converter (DAC) circuitry; and
integrator circuitry coupled to the input circuitry and the DAC circuitry via a pair of second nodes.

2. The CTSD ADC of claim 1 , wherein the amplifier comprises:
a first inverting input coupled to an output of one of the pair of switches;
a second inverting input coupled to an output of the other one of the pair of switches; and
a non-inverting input coupled to a voltage rail set to a target common mode voltage.

3. The CTSD ADC of claim 2 , wherein the amplifier comprises a first output and a second output, and wherein the amplifier is further to provide the common mode signal including:
a first common mode signal at the first output of the amplifier, the first output connected directly to one of the pair of first nodes; and
a second common mode signal at the second output of the amplifier, the second output connected directly to the other one of the pair of first nodes.

4. The CTSD ADC of claim 2 , wherein the amplifier comprises a single output, wherein the input circuitry further comprises
a pair of resistors, each connected between a corresponding one of the pair of first nodes and the single output of the amplifier.

5. The CTSD ADC of claim 1 , wherein the input circuitry comprises a resistive network comprising a plurality of resistive elements including the pair of switches, and wherein one or more of the plurality of resistive elements are sized to provide, for a full-scale input, a current flowing from the input circuitry into the pair of second nodes with an amount substantially the same as a feedback current generated by the DAC circuitry for a full-scale codeword.

6. The CTSD ADC of claim 5 , wherein the pair of switches are sized to provide, for a full-scale input, the current flowing from the input circuitry into the pair of second nodes with the amount substantially the same as the feedback current generated by the DAC circuitry for the full-scale codeword.

7. The CTSD ADC of claim 1 , further comprising:
level-shifter circuitry coupled to the pair of second nodes,
wherein the input circuitry comprises a resistive network comprising a plurality of resistive elements including the pair of switches, and
wherein one or more of the plurality of resistive elements are sized to provide, for a full-scale input, a current flowing from the input circuitry into the pair of second nodes with an amount substantially the same as a sum of a feedback current generated by the DAC circuitry for a full-scale codeword and a current provided by the level-shifter circuitry.

8. The CTSD ADC of claim 7 , wherein the pair of switches are sized to provide the current flowing from the input circuitry into the pair of second nodes with the amount substantially the same as the sum of the feedback current generated by the DAC circuitry for the full-scale codeword and the current provided by the level-shifter circuitry.

9. The CTSD ADC of claim 1 , wherein the input circuitry comprises a resistive network comprising a plurality of resistive elements including the pair of switches, and wherein the CTSD ADC further comprises:
negative resistance circuitry to provide a negative resistance based on a resistance of the resistive network in the input circuitry.

10. The CTSD ADC of claim 1 , further comprising:
level-shifter circuitry coupled to the pair of second nodes, the level-shifter circuitry comprising a first switch and a first resistor coupled to one of a reference voltage or a ground potential,
wherein the input circuitry comprises a resistive network comprising a plurality of resistive elements including the pair of switches,
wherein an output of the amplifier is coupled to the first switch via a second resistor, and
wherein the second resistor is sized to provide, for a full-scale input, a current flowing from the input circuitry into the pair of second nodes with an amount substantially the same as a sum of a feedback current generated by the DAC circuitry for a full-scale codeword and a current provided by the level-shifter circuitry.

11. The CTSD ADC of claim 1 , wherein the amplifier comprises:
an inverting input coupled to the pair of input nodes; and
a non-inverting input coupled to a voltage rail set to a target common mode voltage.

12. The CTSD ADC of claim 1 , wherein the CTSD ADC is a multi-bit ADC, wherein the DAC circuitry comprises at least a first current steering element connected in parallel with a second current steering element, wherein the input circuitry comprises a first resistive network connected in parallel with a second resistive network, wherein a resistance of the first resistive network is based on a resistance of the first current steering element, and wherein a resistance of the second resistive network is based on a resistance of the second current steering element.

13. An input circuitry in an integrated single-ended continuous time sigma delta (CTSD) analog-to-digital converter (ADC) device, the input circuitry comprising:
a pair of input nodes to receive a single-ended input signal;
a first signal path coupled to one of the pair of input nodes, the first signal path comprising a first resistor coupled to an input of a first switch via a first node;
a second signal path coupled to the other one of the pair of input nodes, the second signal path comprising a second resistor coupled to an input of a second switch via a second node; and
a common mode amplifier to inject a common mode current signal to the first node and the second node to provide a differential signal across the input of the first switch and the input of the second switch.

14. The input circuitry of claim 13 , wherein the common mode amplifier comprises:
a first inverting input coupled to an output of the first switch;
a second inverting input coupled to an output of the second switch; and
a non-inverting input coupled to a voltage rail set to a target common mode voltage.

15. The input circuitry of claim 14 , wherein the common mode amplifier comprises a first output and a second output, and wherein the common mode amplifier is further to provide the common mode current signal including:
a first common mode current signal at the first output of the common mode amplifier, the first output connected directly to the first node; and
a second common mode current signal at the second output of the common mode amplifier, the second output connected directly to the second node.

16. The input circuitry of claim 14 , wherein the common mode amplifier comprises a single output, wherein the input circuitry further comprises
a third resistor connected between the first node and the single output of the common mode amplifier; and
a fourth resistor connected between the second node and the single output of the common mode amplifier.

17. A method for performing a continuous time sigma delta (CTSD) analog-to-digital conversion on a single-ended input signal, the method comprising:
receiving, at a pair of input nodes, the single-ended input signal;
converting the single-ended input signal into a differential signal, wherein the converting comprises injecting a common mode signal into inputs of a pair of switches, ea

Assignees

• Analog Devices International Unlimited Co

Inventors

• Maurino Roberto Sergio Matteo
• Srikanth Nittala Venkata Aruna
• Vyas Bhargav R
• Hurrell Christopher Peter
• Thomas Andrew J

Classifications

• H03M1/1245

  Details of sampling arrangements or methods · CPC title

• H03M3/464 Primary

  Details of the digital/analogue conversion in the feedback path · CPC title

• H03M3/326

  by averaging out the errors · CPC title

• H03M3/424

  the quantiser being a multiple bit one · CPC title

• H03M3/454

  with distributed feedback, i.e. with feedback paths from the quantiser output to more than one filter stage · CPC title