Dynamic comparator

Patent metadata

Field	Value
Publication number	US-11545992-B2
Application number	US-202117450598-A
Country	US
Kind code	B2
Filing date	Oct 12, 2021
Priority date	Dec 9, 2020
Publication date	Jan 3, 2023
Grant date	Jan 3, 2023

Abstract

The present description relates to a comparator (2) comprising a ring of gates (110A, 110B, 110A′, 110B′, 106, 108) in series, wherein: each gate implements an inverting function between a first input (100) and an output (102) of the gate; at least one (110A′, 110B′) gate is controllable and is associated with another gate; each controllable gate (110A′, 110B′) comprises a control input (116) coupled with the output (102) of said associated gate, and prevents switching of its output (102) to a high state if its control input (116) is in the high state, and to a low state otherwise; and the control input (116) of each controllable gate (110A′, 110B′) receives the output (102) of said associated gate if an even number of gates separates these two gates, and receives the complement of said output if not.

First claim

What is claimed is:

1. A dynamic comparator of a first voltage with a second voltage, of the edge pursuit type, comprising a ring of logic gates in series, wherein:
each gate of the ring comprises a first input connected to an output of the preceding gate of the ring;
each gate of the ring is configured to implement an inverting function between its first input and its output;
at least one of said gates of the ring is controllable and is associated with another one of said gates of the ring;
each controllable gate comprises a control input coupled to the output of the gate associated with said controllable gate;
each controllable gate is configured to prevent switching of its output to a high state when its control input is in the high state, and to a low state when its control input is in the low state;
the control input of each controllable gate is configured to receive the state of the output of the gate associated with said controllable gate if an even number of gates of the ring separates the controllable gate from said associated gate, and to receive the complementary state of said output if not; and
the ring has an even number of logic gates.

2. The comparator according to claim 1 , wherein each controllable gate is separated from the gate associated with the controllable gate by at least one of said gates of the ring.

3. The comparator according to claim 1 , wherein a number of gates of the ring separating each controllable gate from the gate associated with said controllable gate is strictly less than half the total number of gates of the ring minus one.

4. The comparator according to claim 1 , wherein:
said gates of the ring comprise a first logic gate, a second logic gate, and third and fourth logic gates;
a first branch of the ring comprises alternating third and fourth gates in series between the output of the first gate and the first input of the second gate, the first branch beginning with a third gate;
a second branch of the ring comprises alternating third and fourth gates in series between the output of the second gate and the first input of the first gate, the second branch beginning with a fourth gate; and
each of the third and fourth gates is polarized from the first voltage and/or from the second voltage, the polarization of the third gates being complementary to that of the fourth gates, the polarization of each of the third and fourth gates determining a switching speed of the output of said gate to the high state and a switching speed of the output of said gate to the low state.

5. The comparator according to claim 4 , wherein each branch includes a same number of third gates and each branch includes a same number of fourth gates.

6. The comparator according to claim 4 , wherein:
each of the third and fourth gates comprises a first polarization node and a second polarization node, for example combined with the first node, a voltage on the first node determining the switching speed of the output of said gate to the high state and a voltage on the second node determining the switching speed of the output of said gate to the low state;
the first nodes of the third gates are configured to receive the first voltage or the second voltage, the first nodes of the fourth gates being configured to receive the second voltage when the first nodes of the third gates receive the first voltage, or the first voltage when the first nodes of the third gates receive the second voltage; and
the second nodes of the third gates are configured to receive the first voltage or the second, the second nodes of the fourth gates being configured to receive the second voltage when the second nodes of the third gates receive the first voltage, or the first voltage when the second nodes of the third gates receive the second voltage.

7. The comparator according to claim 1 , wherein each controllable gate comprises:
a first MOS transistor connecting the output of the controllable gate to a node for applying a high potential, the first transistor having a gate connected to the control input of the controllable gate and being configured, in the off state, to electrically isolate the output of the controllable gate from the node for applying the high potential; and
a second MOS transistor connecting the output of the gate to a node for applying a low potential, the second transistor having a gate connected to the control input of the controllable gate and being configured, in the off state, to electrically isolate the output of the controllable gate from the node for applying the low potential.

8. The comparator according to claim 6 , wherein each of the third and fourth gates comprises:
at least one first MOS transistor configured to switch the output of said gate to the high state when the first input of said gate receives a falling edge, said at least one first transistor being polarized from the voltage on the first node of said gate; and
at least one second MOS transistor configured to switch the output of said gate to the low state when the first input of said gate receives a rising edge, said at least one second transistor being polarized from the voltage on the second node of said gate.

9. The comparator according to claim 8 , wherein each of the third and fourth gates comprises a single first transistor and a single second transistor.

10. The comparator according to claim 8 , wherein, in each of the third and fourth gates:
said at least one first transistor is in series with a transistor having a gate connected to the first node of said gate and said at least one second transistor is in series with another transistor having a gate connected to the second node of said gate; or
said at least one first transistor and said at least one second transistor are implemented on silicon on insulator, for example completely depleted, a back gate of each first transistor being connected to the first node of said gate and a back gate of each second transistor being connected to the second node of said gate.

11. The comparator according to claim 8 , wherein each controllable gate is one of the third and fourth gates and further comprises a third MOS transistor configured, in the off state, to electrically isolate the output of said controllable gate from a node for applying a supply voltage, and a fourth MOS transistor configured, in the off state, to electrically isolate the output of said controllable gate from a node for applying a reference voltage, a gate of each of the third and fourth transistors being connected to the control input of said controllable gate.

12. The comparator according to claim 5 , wherein the first and second branches and symmetrical.

13. The comparator according to claim 5 , wherein each of the first and second gates further comprises a second input configured to receive a synchronization signal, the implementation of the inverting function between the first input and the output of said gate being conditioned by the state of the synchronization signal.

14. The comparator according to claim 5 , wherein, for each controllable gate, the gate associated with said controllable gate is the first gate or one of the third and fourth gates of the first branch when said controllable gate belongs to the first branch, and is the second gate or one of the third and fourth gates of the second branch when said controllable gate belongs to the second branch.

15. An analog-digital converter comprising a comparator according to claim 1 .

Assignees

• Commissariat Energie Atomique

Inventors

• Verdant Arnaud

Classifications

• H03M1/12

  Analogue/digital converters ({H03M1/001 – } H03M1/10 take precedence) · CPC title

• H03K5/2472 Primary

  using field effect transistors (H03K5/2436 takes precedence) · CPC title

• H03M1/804

  with charge redistribution · CPC title

• G06F7/02

  Comparing digital values (G06F7/06, {G06F7/22,} G06F7/38 take precedence) · CPC title

• H03M1/42 Primary

  Sequential comparisons in series-connected stages with no change in value of analogue signal · CPC title