Bleeder circuitry for an electronic device

Patent metadata

Field	Value
Publication number	US-11545940-B2
Application number	US-202117243762-A
Country	US
Kind code	B2
Filing date	Apr 29, 2021
Priority date	Apr 29, 2021
Publication date	Jan 3, 2023
Grant date	Jan 3, 2023

Abstract

Devices and methods include voltage buses. The devices also include one or more power amplifiers coupled to the voltage bus. Each of the one or more power amplifiers include one or more transistors. The devices also include a model that is configured to emulate leakage from at least one of the one or more transistors. A current mirror with a first transistor coupled to the model and a second transistor coupled to the voltage bus. The current mirror is configure to draw charge from the voltage bus based at least in part on the emulated leakage from the model.

First claim

What is claimed is:

1. A semiconductor device comprising:
a voltage bus;
one or more power amplifiers coupled to the voltage bus, wherein each of the one or more power amplifiers comprises one or more transistors;
a model that is configured to emulate leakage from at least one of the one or more transistors; and
a current mirror with a first transistor coupled to the model and a second transistor coupled to the voltage bus, wherein the current mirror is configured to draw charge from the voltage bus based at least in part on the emulated leakage from the model, wherein a gate of the first transistor is coupled to a gate of the second transistor and a drain of the second transistor.

2. The semiconductor device of claim 1 , wherein the model comprises an emulation transistor configured to produce a leakage current through the transistor that is configured to emulate leakage from a power amplifier transistor of the one or more transistors of a power amplifier of the one or more power amplifiers.

3. The semiconductor device of claim 2 , wherein the leakage current is greater than or equal to the leakage from the power amplifier transistor.

4. The semiconductor device of claim 2 , wherein the power amplifier transistor emulates the leakage when the power amplifier transistor is in or transitions to a standby mode.

5. The semiconductor device of claim 1 , wherein the second transistor is N times larger than the first transistor where N is a number of the one or more power amplifiers to have leakage mitigated.

6. The semiconductor device of claim 1 , comprising an additional current mirror coupled to the current mirror, wherein the additional current mirror comprises a third transistor coupled to the first transistor and a fourth transistor coupled to the second transistor.

7. The semiconductor device of claim 6 , wherein the first and second transistors comprise p-channel metal oxide semiconductors.

8. The semiconductor device of claim 7 , wherein the third and fourth transistors comprise n-channel metal oxide semiconductors.

9. The semiconductor device of claim 6 , wherein a gate of the fourth transistor is coupled to a gate and drain of the third transistor.

10. The semiconductor device of claim 6 , wherein a drain of the first transistor is coupled to a drain of the third transistor, and the drain of the second transistor is coupled to a drain of the fourth transistor.

11. The semiconductor device of claim 6 , comprising startup transistor between a node of the current mirror and a node of the additional current mirror to balance operation of the current mirror and the additional current mirror during startup of the semiconductor device.

12. The semiconductor device of claim 11 , wherein the node of the current mirror is coupled to the gate of the first transistor and the gate and the drain of the second transistor, and the node of the additional current mirror is coupled to a gate of the fourth transistor and a gate and drain of the third transistor.

13. The semiconductor device of claim 6 , wherein the fourth transistor is N times larger than the third transistor where N is a number of the one or more power amplifiers to have leakage mitigated.

14. The semiconductor device of claim 6 , wherein the current mirror and additional current mirror consume different amounts of current for different process corners.

15. A method, comprising:
generating, using a model transistor, a modeled leakage current that models a leakage current in a transistor of a power amplifier;
transmitting the modeled leakage current to a first leg of a plurality of current mirrors coupled in series; and
using a second leg of the plurality of current mirrors coupled to a voltage bus, mitigating changes to the voltage bus due to leakage currents from a plurality of power amplifiers using a compensation current at the second leg that is based at least in part on the modeled leakage current.

16. The method of claim 15 , wherein generating the modeled leakage current comprises placing the model transistor in a same state as the transistor when the model transistor is equal in size to the transistor and has a same type as the model transistor.

17. The method of claim 16 , wherein the state comprises an off state.

18. A device, comprising:
a voltage bus;
a plurality of power amplifiers each comprising a transistor;
a model transistor configured to generate a modeled current leakage that emulates a leakage of the transistor of one of the plurality of power amplifiers; and
a plurality of current mirrors with respective first and second legs coupled in series between each of the plurality of current mirrors, wherein the plurality of current mirrors is configured to receive the modeled current leakage at a respective first leg of a current mirror of the plurality of current mirrors and to generate a compensation current at a respective second leg of the current mirror based on the modeled current leakage that mitigates voltage fluctuations on the voltage bus due to leakages from the plurality of power amplifiers.

19. The device of claim 18 , wherein each current mirror comprises a first transistor in the respective first leg and a second transistor in the respective second leg, wherein each second transistor is N times larger than the respective first transistor of the same current mirror where N is the number of power amplifiers in the plurality of power amplifiers.

20. The device of claim 18 , comprising a startup transistor coupled between two of the plurality of current mirrors.

21. The device of claim 18 , wherein the model transistor is configured to model the current leakage when the transistor is in a standby state.

Assignees

• Micron Technology Inc

Inventors

• Chu Wei Lu
• Pan Dong

Classifications

• G05F3/262

  using field-effect transistors only · CPC title

• H03F3/45273

  Mirror types · CPC title

• H03F1/301 Primary

  in MOSFET amplifiers (H03F1/303, H03F1/305, H03F1/308 take precedence) · CPC title

• H03F3/213

  in integrated circuits · CPC title

• H03F3/45112

  Complementary long tailed pairs having parallel inputs and being supplied in parallel · CPC title