Gate driver power-saving method for switched-mode power supplies in pulse-skipping mode

Patent metadata

Field	Value
Publication number	US-11545897-B2
Application number	US-202017021591-A
Country	US
Kind code	B2
Filing date	Sep 15, 2020
Priority date	Sep 17, 2019
Publication date	Jan 3, 2023
Grant date	Jan 3, 2023

Abstract

Techniques and apparatus for controlling gate drivers of a switched-mode power supply (SMPS) circuit—such as a three-level buck converter, a divide-by-two charge pump, or an adaptive combination power supply circuit capable of switching therebetween—in a power-saving mode (e.g., a pulse-skipping mode). During such a power-saving mode in which a capacitor of a charge pump is disconnected from at least one power supply rail (e.g., first and second input nodes of the charge pump) and is coupled to power terminals of one or more drivers of the SMPS circuit, the capacitor is temporarily disconnected from the power terminals and temporarily coupled to the at least one power supply rail (e.g., for a few microseconds).

First claim

What is claimed is:

1. A power supply circuit comprising:
a switched-mode power supply (SMPS) circuit having a first input voltage node and a second input voltage node; and
a charge pump comprising:
a first capacitive element having a first terminal and a second terminal;
a first switch coupled between a first input node of the charge pump and the first terminal of the first capacitive element;
a second switch coupled between the second terminal of the first capacitive element and a second input node of the charge pump;
a third switch coupled between the first terminal of the first capacitive element and the first input voltage node of the SMPS circuit; and
a fourth switch coupled between the second terminal of the first capacitive element and the second input voltage node of the SMPS circuit, wherein:
in a first phase, the first and second switches are configured to be closed, and the third and fourth switches are configured to be open;
in a second phase, the third and fourth switches are configured to be closed, and the first and second switches are configured to be open; and
the power supply circuit is configured to operate the charge pump in the second phase in a power-saving mode and configured to temporarily operate the charge pump in the first phase in the power-saving mode to recharge the first capacitive element.

2. The power supply circuit of claim 1 , further comprising a comparator having a first input coupled to the first terminal of the first capacitive element and a second input coupled to the second terminal of the first capacitive element.

3. The power supply circuit of claim 2 , wherein the charge pump is configured, during the power-saving mode, to operate in the second phase until a difference between voltages at the first and second inputs of the comparator falls below a threshold voltage and is configured to temporarily enter the first phase in response to the voltages at the first and second inputs of the comparator falling below the threshold voltage.

4. The power supply circuit of claim 1 , wherein the charge pump is configured, during the power-saving mode, to periodically temporarily operate in the first phase according to a constant interval.

5. The power supply circuit of claim 1 , further comprising a voltage regulator having a first input coupled to a third input voltage node of the SMPS circuit and having an output coupled to the first input node of the charge pump.

6. The power supply circuit of claim 5 , wherein:
the voltage regulator has a second input coupled to an output voltage node of the SMPS circuit; and
the voltage regulator is configured to select between the first input and the second input for supplying current to drive the SMPS circuit.

7. The power supply circuit of claim 1 , wherein the SMPS circuit comprises:
a first transistor;
a second transistor coupled to the first transistor via a first node;
a third transistor coupled to the second transistor via a second node;
a fourth transistor coupled to the third transistor via a third node;
a second capacitive element having a first terminal coupled to the first node and a second terminal coupled to the third node; and
an inductive element having a first terminal coupled to the second node and a second terminal coupled to an output voltage node of the SMPS circuit.

8. The power supply circuit of claim 7 , wherein the SMPS circuit further comprises a fifth switch having a first terminal coupled to the first terminal of the inductive element and having a second terminal coupled to the second terminal of the inductive element.

9. The power supply circuit of claim 7 , wherein:
a drain of the second transistor is coupled to a source of the first transistor;
a drain of the third transistor is coupled to a source of the second transistor; and
a drain of the fourth transistor is coupled to a source of the third transistor.

10. The power supply circuit of claim 9 , wherein:
a drain of the first transistor is coupled to a third input voltage node of the SMPS circuit;
the first node of the SMPS circuit is coupled to the second input voltage node; and
a source of the fourth transistor is coupled to a reference potential node of the SMPS circuit.

11. The power supply circuit of claim 7 , wherein the SMPS circuit further comprises:
a first driver having an output coupled to a gate of the first transistor;
a second driver having an output coupled to a gate of the second transistor;
a third driver having an output coupled to a gate of the third transistor; and
a fourth driver having an output coupled to a gate of the fourth transistor.

12. The power supply circuit of claim 11 , wherein:
the first driver has a first power terminal coupled to the first input voltage node of the SMPS circuit and the third switch of the charge pump; and
the first driver has a second power terminal coupled to the second input voltage node of the SMPS circuit, the first node of the SMPS circuit, and the fourth switch of the charge pump.

13. The power supply circuit of claim 12 , further comprising a third capacitive element coupled between the first and second power terminals of the first driver.

14. The power supply circuit of claim 11 , further comprising a first clamping supply having an input coupled to the first input voltage node of the SMPS circuit and to the third switch of the charge pump, a first output coupled to a first power terminal of the second driver, and a second output coupled to a second power terminal of the second driver and to the second node of the SMPS circuit.

15. The power supply circuit of claim 14 , further comprising a second clamping supply having an input coupled to the first input voltage node of the SMPS circuit and to the third switch of the charge pump, having a first output coupled to a first power terminal of the third driver, and having a second output coupled to a second power terminal of the third driver and to the third node of the SMPS circuit.

16. The power supply circuit of claim 11 , wherein:
the fourth driver has a first power terminal coupled to the first input node of the charge pump and to the first switch of the charge pump; and
the fourth driver has a second power terminal coupled to a reference potential node of the SMPS circuit and to a source of the fourth transistor.

17. The power supply circuit of claim 1 , wherein the SMPS circuit comprises a three-level buck converter.

18. A power management integrated circuit (PMIC) comprising at least a portion of the power supply circuit of claim 1 .

19. A battery charging circuit comprising the power supply circuit of claim 1 .

20. A method of supplying power, comprising:
operating a power supply circuit comprising:
a switched-mode power supply (SMPS) circuit having a first input voltage node and a second input voltage node; and
a charge pump comprising:
a capacitive element having a first terminal and a second terminal;
a first switch coupled between a first input node of the charge pump and the first terminal of the capacitive element;
a second switch coupled between the second terminal of the capacitive element and a second input node of the charge pump;
a third switch coupled between the first terminal of the capacitive element and the first input voltage node of the SMPS circuit; and
a fourth switch coupled between the second terminal of the capacitive element and the second input voltage node of the SMPS circuit, wherein the operating comprises:
in a first phase, closing the first and second switches a

Assignees

• Qualcomm Inc

Inventors

• Yen Ta-Tung
• Guo Guoyong
• Song Chunping
• Oporta Hector Ivan

Classifications

• H02M1/0032

  Control circuits allowing low power mode operation, e.g. in standby mode · CPC title

• H02M1/0006

  Arrangements for supplying an adequate voltage to the control circuit of converters · CPC title

• Y02B70/10

  Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes · CPC title

• H02M3/158

  including plural semiconductor devices as final control devices for a single load · CPC title

• H02J2207/20

  Charging or discharging characterised by the power electronics converter · CPC title