Superjunction device with oxygen inserted Si-layers

Patent metadata

Field	Value
Publication number	US-11545545-B2
Application number	US-202016930500-A
Country	US
Kind code	B2
Filing date	Jul 16, 2020
Priority date	Nov 9, 2018
Publication date	Jan 3, 2023
Grant date	Jan 3, 2023

Abstract

A semiconductor device includes a source region and a drain region of a first conductivity type, a body region of a second conductivity type between the source region and the drain region, a gate configured to control current through a channel of the body region, a drift zone of the first conductivity type between the body region and the drain region, a superjunction structure formed by a plurality of regions of the second conductivity type laterally spaced apart from one another by intervening regions of the drift zone, and a diffusion barrier structure disposed along sidewalls of the regions of the second conductivity type of the superjunction structure. The diffusion barrier structure includes alternating layers of Si and oxygen-doped Si and a Si capping layer on the alternating layers of Si and oxygen-doped Si.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a source region and a drain region of a first conductivity type;
a body region of a second conductivity type between the source region and the drain region;
a gate configured to control current through a channel of the body region;
a drift zone of the first conductivity type between the body region and the drain region;
a superjunction structure formed by a plurality of regions of the second conductivity type laterally spaced apart from one another by intervening regions of the drift zone; and
a diffusion barrier structure disposed along sidewalls of the plurality of regions of the second conductivity type, the diffusion barrier structure comprising alternating layers of Si and oxygen-doped Si and a Si capping layer adjacent the alternating layers of Si and oxygen-doped Si.

2. The semiconductor device of claim 1 , wherein the diffusion barrier structure is also disposed along a bottom face of the plurality of regions of the second conductivity type.

3. The semiconductor device of claim 1 , wherein the drift zone contacts a bottom face of the plurality of regions of the second conductivity type.

4. The semiconductor device of claim 1 , wherein the drain region is formed in a Si substrate, wherein the drift zone is disposed in a first Si epitaxial layer formed over the Si substrate, and wherein the source region and the body region are disposed in a second Si epitaxial layer formed over the first Si epitaxial layer.

5. The semiconductor device of claim 4 , wherein the gate is a trench gate formed in the second Si epitaxial layer.

6. The semiconductor device of claim 4 , wherein the gate is a planar gate formed on a surface of the second Si epitaxial layer facing away from the first Si epitaxial layer.

7. The semiconductor device of claim 4 , further comprising a contact in electrical contact with the source region and the body region in the second Si epitaxial layer.

8. The semiconductor device of claim 7 , wherein the contact vertically extends through the second Si epitaxial layer, into the first Si epitaxial layer and electrically contacts a region of the plurality of regions of the second conductivity type, and wherein sidewalls of the contact are laterally separated from the second Si epitaxial layer and the first Si epitaxial layer by an insulating material.

9. The semiconductor device of claim 4 , wherein the second Si epitaxial layer contacts a top face of the plurality of regions of the second conductivity type.

10. A semiconductor device, comprising:
a first region and a second region of a first conductivity type;
a first region of a second conductivity type between the first region and the second region of the first conductivity type;
a gate configured to control a channel current in the first region of the second conductivity type;
a third region of the first conductivity type between the first region of the second conductivity type and the second region of the first conductivity type;
a superjunction structure comprising alternating regions of the first conductivity type and the second conductivity type; and
a diffusion barrier structure disposed along sidewalls of the regions of the second conductivity type of the superjunction structure, the diffusion barrier structure comprising alternating layers of Si and oxygen-doped Si and a Si capping layer adjacent the alternating layers of Si and oxygen-doped Si.

11. The semiconductor device of claim 10 , wherein the diffusion barrier structure is also disposed along a bottom face of the regions of the second conductivity type of the superjunction structure.

12. The semiconductor device of claim 10 , wherein the third region of the first conductivity type contacts a bottom face of the regions of the second conductivity type of the superjunction structure.

13. The semiconductor device of claim 10 , wherein the second region of the first conductivity type is formed in a Si substrate, wherein the third region of the first conductivity type is disposed in a first Si epitaxial layer formed over the Si substrate, and wherein the first region of the first conductivity type and the first region of the second conductivity type are disposed in a second Si epitaxial layer formed over the first Si epitaxial layer.

14. The semiconductor device of claim 13 , wherein the gate is a trench gate formed in the second Si epitaxial layer.

15. The semiconductor device of claim 13 , wherein the gate is a planar gate formed on a surface of the second Si epitaxial layer facing away from the first Si epitaxial layer.

16. The semiconductor device of claim 13 , further comprising a contact in electrical contact with the first region of the first conductivity type and the first region of the second conductivity type in the second Si epitaxial layer.

17. The semiconductor device of claim 16 , wherein the contact vertically extends through the second Si epitaxial layer, into the first Si epitaxial layer and electrically contacts a region of the second conductivity type of the superjunction structure, and wherein sidewalls of the contact are laterally separated from the second Si epitaxial layer and the first Si epitaxial layer by an insulating material.

18. The semiconductor device of claim 13 , wherein the second Si epitaxial layer contacts a top face of the regions of the second conductivity type of the superjunction structure.

19. A semiconductor device, comprising:
a source region and a drain region of a first conductivity type;
a body region of a second conductivity type;
a gate configured to control a channel current in the body region;
a drift zone of the first conductivity type;
a superjunction structure formed by a plurality of regions of the second conductivity type spaced apart from one another by intervening regions of the drift zone; and
a diffusion barrier structure disposed at least partly along the regions of the second conductivity type of the superjunction structure, the diffusion barrier structure comprising alternating layers of Si and oxygen-doped Si and a Si capping layer adjacent the alternating layers of Si and oxygen-doped Si.

20. The semiconductor device of claim 19 , wherein the drain region is formed in a Si substrate, wherein the drift zone is disposed in a first Si epitaxial layer formed over the Si substrate, and wherein the source region and the body region are disposed in a second Si epitaxial layer formed over the first Si epitaxial layer.

Assignees

• Infineon Technologies Austria Ag

Inventors

• Poelzl Martin
• Haase Robert
• Leomant Sylvain
• Roesch Maximilian
• Joshi Ravi Keshav
• Meiser Andreas
• Huang Xiaoqiu
• Ma Ling

Classifications

• H01L29/0696

  Electricity · mapped topic

• H01L29/0882

  Electricity · mapped topic

• H01L29/7813

  Electricity · mapped topic

• H01L29/4236

  Electricity · mapped topic

• H01L29/1095

  Electricity · mapped topic