OTP memory and method for making the same

Patent metadata

Field	Value
Publication number	US-11545498-B2
Application number	US-202017111099-A
Country	US
Kind code	B2
Filing date	Dec 3, 2020
Priority date	Dec 26, 2019
Publication date	Jan 3, 2023
Grant date	Jan 3, 2023

Abstract

The present application discloses an OTP memory. A cell structure includes a first active region and a second active region that intersect vertically; an EDNMOS is formed in the first active region, and a PMOS is formed in the second active region; a body portion of a channel region of the PMOS is formed a drift region of the EDNMOS, a first polysilicon gate of the EDNMOS serves as a control gate, and a second polysilicon gate of the PMOS serves as a floating gate; and the PMOS is programmed by means of hot carriers generated in the drift region of the EDNMOS. The present application further discloses a method for manufacturing an OTP memory. In the present application, high-speed writing can be implemented.

First claim

What is claimed is:

1. An OTP memory, wherein a cell structure of the OTP memory comprises:
a first active region and a second active region;
the first active region and the second active region intersect vertically;
an EDNMOS is formed in the first active region, and a PMOS is formed in the second active region;
the EDNMOS comprises a first source region, a first channel region, a drift region, a first drain region, and a first gate structure, the first gate structure is formed by stacking a first gate dielectric layer and a first polysilicon gate, the direction from the first source region to the first drain region is a first direction, the doping types of the first source region, the drift region, and the first drain region are N-type, and the doping type of the first channel region is P-type;
the PMOS comprises a second source region, a second channel region, a second drain region, and a second gate structure, the second gate structure is formed by stacking a second gate dielectric layer and a second polysilicon gate, the direction from the second source region to the second drain region is a second direction, the first direction is perpendicular to the second direction, the doping types of the second source region and the second drain region are P-type, and the doping type of the second channel region is N-type;
the second polysilicon gate covers an overlap region of the first active region and the second active region and extends into the first active region and the second region that are outside the overlap region, in the first direction, the second polysilicon gate has a first side and a second side, and in the second direction, the second polysilicon gate has a third side and a fourth side;
the first side and the second side of the second polysilicon gate are located between a second side of the first polysilicon gate and a first side of the first drain region;
doping of the drift region is also formed in the second active region, and a doping region of the drift region in the second active region covered by the second polysilicon gate and located in the overlap region and outside the overlap region forms the second channel region;
the first source region is self-aligned with a first side of the first polysilicon gate, and the first drain region is self-aligned with the second side of the second polysilicon gate;
the second source region is formed in the second active region and is self-aligned with the third side of the second polysilicon gate, and the second drain region is formed in the second active region and is self-aligned with the fourth side of the second polysilicon gate;
the first polysilicon gate serves as a control gate, and the second polysilicon gate serves as a floating gate; and
the PMOS is programmed by means of injection of hot carriers, the hot carriers being generated in the drift region when the EDNMOS is conducting.

2. The OTP memory according to claim 1 , wherein the first channel region is formed by a P-well, and the first source region is formed in the P-well.

3. The OTP memory according to claim 2 , wherein the first drain region is formed in an N-well.

4. The OTP memory according to claim 3 , wherein lateral coverage of an N-type ion implantation region of the drift region is greater than lateral coverage of the N-well, a first side of the N-well is located between the first side and the second side of the second polysilicon gate, and a body region where the hot carriers are injected is located on the first side of the N-well.

5. The OTP memory according to claim 1 , wherein the outside of the first active region and the second active region is surrounded by a field oxide.

6. The OTP memory according to claim 1 , wherein the first source region, the first drain region, the first polysilicon gate, the second source region, and the second drain region are each connected to a corresponding electrode formed by a front metal layer by means of a contact hole.

7. The OTP memory according to claim 6 , wherein reading from the cell structure of the OTP memory is implemented by applying a voltage between the second source region and the second drain region.

8. A method for manufacturing an OTP memory, wherein manufacturing of a cell structure of the OTP memory comprises steps of:
step 1: defining a first active region and a second active region on a semiconductor substrate by means of a field oxide,

wherein the first active region and the second active region intersect vertically;
step 2: respectively forming a first channel region of an EDNMOS in the first active region, wherein the doping type of the first channel region is P-type;
step 3: forming a drift region of the EDNMOS in the first active region, wherein the drift region is in lateral contact with the first channel region; doping of the drift region is also formed in the second active region; and

the doping type of the drift region is N-type;
step 4: simultaneously forming a first gate structure of the EDNMOS and a second gate structure of a PMOS,
wherein the first gate structure is formed by stacking a first gate dielectric layer and a first polysilicon gate, and the second gate structure is formed by stacking a second gate dielectric layer and a second polysilicon gate;
the first polysilicon gate covers the surface of the first channel region, and a second side of the first polysilicon gate extends above the drift region;
the second polysilicon gate covers an overlap region of the first active region and the second active region and extends into the first active region and the second region that are outside the overlap region; and a doping region of the drift region in the second active region covered by the second polysilicon gate and located in the overlap region and outside the overlap region forms a second channel region of the PMOS; and
step 5: performing N+ source-drain implantation to form a first source region and a first drain region of the EDNMOS, and performing P+ source-drain implantation to form a second source region and a second drain region of the PMOS,
wherein the direction from the first source region to the first drain region is a first direction, the direction from the second source region to the second drain region is a second direction, and the first direction is perpendicular to the second direction;
in the first direction, the second polysilicon gate has a first side and a second side, and in the second direction, the second polysilicon gate has a third side and a fourth side;
the first side and the second side of the second polysilicon gate are located between the second side of the first polysilicon gate and a first side of the first drain region;
the first source region is self-aligned with a first side of the first polysilicon gate, and the first drain region is self-aligned with the second side of the second polysilicon gate;
the second source region is formed in the second active region and is self-aligned with the third side of the second polysilicon gate, and the second drain region is formed in the second active region and is self-aligned with the fourth side of the second polysilicon gate;
the first polysilicon gate serves as a control gate, and the second polysilicon gate serves as a floating gate; and
the PMOS is programmed by means of injection of hot carriers, the hot carriers being generated in the drift region when the EDNMOS is conducting.

9. The method for manufacturing an OTP memory according to claim 8 , wherein in step 2, a P-well is formed by means of a P-well formation process, the first channel region is formed by the P-well, and the first source region is formed in the P-well.

10. The method for manufacturing an OTP memory according to claim

Assignees

• Hua Hong Semiconductor Wuxi Ltd
• Shanghai Huahong Grace Semiconductor Mfg Corp

Inventors

• Liu Junwen
• Chen Hualun

Classifications

• H10P30/204

  into Group IV semiconductors · CPC title

• H10P30/21 Primary

  of electrically active species · CPC title

• G11C16/0433

  comprising cells containing a single floating gate transistor and one or more separate select transistors · CPC title

• G11C17/08

  using semiconductor devices, e.g. bipolar elements (G11C17/06, G11C17/14 take precedence) · CPC title

• H01L29/7885

  Electricity · mapped topic