Integrated circuit with single level routing

Patent metadata

Field	Value
Publication number	US-11545480-B2
Application number	US-201816222670-A
Country	US
Kind code	B2
Filing date	Dec 17, 2018
Priority date	Jun 29, 2018
Publication date	Jan 3, 2023
Grant date	Jan 3, 2023

Abstract

An integrated circuit includes a substrate layer and a resistor bank in a polysilicon layer disposed on the substrate layer. The resistor bank includes a plurality of resistor elements having a body portion extending in a longitudinal direction. A metal line is disposed in a metal layer above the polysilicon layer to extend transverse to the longitudinal direction and across the body portion of a group of the plurality of resistor elements, thereby forming a first region of the resistor bank and a second region of the resistor bank. The first region is separated from the second region by the metal line. A resistor device having a predetermined resistance includes a subset of the resistor elements in the group electrically coupled together in the second region. The resistor device also includes first and second terminals located in the same first or second region of the resistor bank.

First claim

What is claimed is:

1. An integrated circuit comprising:
a substrate layer;
a semiconductor layer on the substrate layer, the semiconductor layer comprising a resistor bank, the resistor bank comprising:
a first resistor having a first end and a second end;
a second resistor having a third end and a fourth end;
a third resistor having a fifth end and a sixth end;
a fourth resistor having a seventh end and an eighth end; and

a metal layer above the semiconductor layer, the metal layer comprising:
a metal line traversing the first resistor, the second resistor, the third resistor, and the fourth resistor;
a first coupling electrically connecting the first end of the first resistor and the seventh end of the fourth resistor;
a second coupling electrically connecting the fifth end of the third resistor and the third end of the second resistor; and
a third coupling electrically connecting the first coupling and the second coupling.

2. The integrated circuit of claim 1 , wherein the first resistor has a resistance, the second resistor has the resistance, the third resistor has the resistance, and the fourth resistor has the resistance.

3. The integrated circuit of claim 1 , wherein the metal layer further comprises a fourth coupling electrically connecting the eighth end of the fourth resistor to the second end of the first resistor.

4. The integrated circuit of claim 3 , wherein the metal layer further comprises a fifth coupling electrically connecting the fourth end of the second resistor to the sixth end of the third resistor.

5. The integrated circuit of claim 4 , wherein a resistance from the fifth coupling to the fourth coupling is a resistance, and the first resistor has the resistance.

6. The integrated circuit of claim 1 , wherein the metal line is a first metal line, the integrated circuit further comprising a second metal line crossing the first resistor, the second resistor, the third resistor, and the fourth resistor.

7. The integrated circuit of claim 1 , wherein the first resistor, the second resistor, the third resistor, and the fourth resistor are in a first column, the resistor bank further comprising a fifth resistor, a sixth resistor, and a seventh resistor in a second column.

8. The integrated circuit of claim 7 , wherein the resistor bank further comprises an eighth resistor, a ninth resistor, and a tenth resistor in a third column.

9. The integrated circuit of claim 1 , wherein the first resistor, the second resistor, the third resistor, and the fourth resistor are bandgap resistors.

10. The integrated circuit of claim 1 , wherein the semiconductor layer is a polysilicon layer.

11. The integrated circuit of claim 1 , wherein a first region is on a first side of the metal line, a second region is on a second side of the metal line, the first end of the first resistor, the third end of the second resistor, the fifth end of the third resistor, and the seventh end of the fourth resistor are in the first region and the second end of the first resistor, the fourth end of the second resistor, the sixth end of the third resistor, and the eighth end of the fourth resistor are in the second region.

12. An integrated circuit comprising:
a semiconductor layer comprising a resistor bank, the resistor bank comprising:
a first resistor having a first end and a second end;
a second resistor having a third end and a fourth end;
a third resistor having a fifth end and a sixth end; and
a fourth resistor having a seventh end and an eighth end; and

a metal layer above the semiconductor layer, the metal layer comprising:
a metal line traversing the first resistor, the second resistor, the third resistor, and the fourth resistor;
a first coupling electrically connecting the first end of the first resistor and the seventh end of the fourth resistor;
a second coupling electrically connecting the fifth end of the third resistor and the third end of the second resistor; and
a third coupling electrically connecting the first coupling and the second coupling.

13. The integrated circuit of claim 12 , wherein the first end of the first resistor, the seventh end of the third resistor, the third end of the second resistor, and the fifth end of the third resistor are on a side of the metal line.

14. The integrated circuit of claim 13 , wherein the side of the metal line is a first side of the metal line, and wherein the eighth end of the fourth resistor, the second end of the first resistor, the fourth end of the second resistor, and the sixth end of the third resistor are on a second side of the metal line.

15. The integrated circuit of claim 12 , the metal layer further comprising:
a fourth coupling electrically connecting the second end of the first resistor to the eighth end of the fourth resistor; and
a fifth coupling electrically connecting the sixth end of the third resistor to the fourth end of the second resistor.

16. The integrated circuit of claim 15 , wherein a resistance from the fourth coupling to the fifth coupling is the same as the resistance of the first resistor.

17. An integrated circuit comprising:
a semiconductor layer comprising a resistor bank, the resistor bank comprising:
a first resistor having a first end and a second end;
a second resistor having a third end and a fourth end;
a third resistor having a fifth end and a sixth end; and
a fourth resistor having a seventh end and an eighth end; and

a metal layer above the semiconductor layer, the metal layer comprising:
a metal line, a first coupling, a second coupling, a third coupling, a fourth coupling, and a fifth coupling, the first coupling electrically connecting the second end of the first resistor and the eighth end of the fourth resistor, the second coupling electrically connecting the sixth end of the third resistor and the fourth end of the second resistor, the third coupling electrically connecting the first end of the first resistor and the seventh end of the fourth resistor, the fourth coupling electrically connecting the fifth end of the third resistor and the third end of the second resistor, and the fifth coupling electrically connecting the third coupling and the fourth coupling.

18. The integrated circuit of claim 17 , wherein the third coupling, the fourth coupling, and the fifth coupling are on a first side of the metal line and the first coupling and the second coupling are on a second side of the metal line.

19. The integrated circuit of claim 17 , wherein a resistance from the second coupling to the third coupling is the same as a resistance of the first resistor.

20. The integrated circuit of claim 1 , wherein the resistor bank further comprises a fifth resistor, the metal line traversing the fifth resistor, the fifth resistor between the first resistor and the third resistor.

Assignees

• Texas Instruments Inc

Inventors

• Gojagoji Sachin Ishwar
• Selvaraj Raja
• Mathad Jayateerth Pandurang
• Kumar Sujay

Classifications

• H01L28/24

  Electricity · mapped topic

• H01L27/101

  Electricity · mapped topic

• H01L2027/11842

  Electricity · mapped topic

• H01L27/0802

  Electricity · mapped topic

• H01L27/1112

  Electricity · mapped topic