Address latch comprising intermediate latch circuit that latches the address data latched by the write latch circuit, display device and address latching method

Patent metadata

Field	Value
Publication number	US-11545197-B2
Application number	US-202016831183-A
Country	US
Kind code	B2
Filing date	Mar 26, 2020
Priority date	Nov 19, 2019
Publication date	Jan 3, 2023
Grant date	Jan 3, 2023

Abstract

An address latch, a display device, and an address latching method are disclosed. The address latch includes a write control circuit, a write latch circuit, a latch control circuit, an intermediate latch circuit, and an output latch circuit. The write latch circuit is configured to latch an address data in response to N write control signals generated by the write control circuit, N data bits of the address data are divided into (M−1) data bit groups; the latch control circuit is configured to sequentially generate M latch control signals; the intermediate latch circuit is configured to, in response to first to (M−1)-th latch control signals, latch first to (M−1)-th data bit groups latched by the write latch circuit in a time-division manner; and the output latch circuit is configured to output the address data latched by the intermediate latch circuit in response to an M-th latch control signal.

First claim

What is claimed is:

1. An address latch, comprising: a write control circuit, a write latch circuit, a latch control circuit, an intermediate latch circuit, and an output latch circuit, wherein
the write control circuit is configured to generate N write control signals, and N is a positive integer greater than or equal to 2;
the write latch circuit is connected to the write control circuit, and is configured to latch an address data that is received in response to the N write control signals, the address data comprises N data bits, and the N data bits are divided into (M−1) data bit groups;
the latch control circuit is configured to sequentially generate M latch control signals, and M is a positive integer greater than or equal to 3;
the intermediate latch circuit is connected to the write latch circuit and the latch control circuit, and is configured to sequentially latch, in response to first to (M−1)-th latch control signals of the M latch control signals, the (M−1) data bit groups of the address data latched by the write latch circuit in a time-division manner;
the output latch circuit is connected to the intermediate latch circuit and the latch control circuit, and is configured to output the address data latched by the intermediate latch circuit from the address latch in response to an M-th latch control signal of the M latch control signals;
the latch control circuit comprises a primary latch control circuit and a secondary latch control circuit;
the primary latch control circuit is configured to generate L primary latch control signals in response to a latch enable signal, a first control signal, and a second control signal;
the secondary latch control circuit is configured to generate L secondary latch control signals in response to the first control signal, the second control signal, and the L primary latch control signals; and
M secondary latch control signals of the L secondary latch control signals are used as the M latch control signals, and L is a positive integer greater than or equal to M.

2. The address latch according to claim 1 , wherein the write latch circuit comprises N write latch sub-circuits,
the N write latch sub-circuits are configured to be sequentially turned on, in response to the N write control signals, respectively, to latch respective data bits of the address data, respectively.

3. The address latch according to claim 2 , wherein each of the N write latch sub-circuits comprises a control terminal, an input terminal, and an output terminal,
the control terminal of each write latch sub-circuit is configured to receive a corresponding write control signal of the N write control signals; and
the input terminal of each write latch sub-circuit is connected to an address data line to receive the address data.

4. The address latch according to claim 3 , wherein the write control circuit comprises N write control sub-circuits, and the N write control sub-circuits are connected to the N write latch sub-circuits in one-to-one correspondence manner,
the N write control sub-circuits are configured to respectively generate the N write control signals in one-to-one correspondence manner.

5. The address latch according to claim 4 , wherein each of the N write control sub-circuits comprises a control terminal, an input terminal, and an output terminal,
the control terminal of each write control sub-circuit is connected to a write clock signal line to receive a write clock signal,
the output terminals of the N write control sub-circuits are connected to the control terminals of the N write latch sub-circuits in one-to-one correspondence manner,
an input terminal of a first write control sub-circuit of the N write control sub-circuits is connected to an output terminal of an N-th write control sub-circuit of the N write control sub-circuits, and an output terminal of an j-th write control sub-circuit of the N write control sub-circuits is connected to an input terminal of an (j+1)-th write control sub-circuit of the N write control sub-circuits, 1<j<N−1, and n is a positive integer.

6. The address latch according to claim 4 , wherein the intermediate latch circuit comprises N intermediate latch sub-circuits, the N intermediate latch sub-circuits are connected to the N write latch sub-circuits in one-to-one correspondence manner, and the N intermediate latch sub-circuits are divided into (M−1) intermediate latch sub-circuit groups,
the (M−1) intermediate latch sub-circuit groups latch the (M−1) data bit groups of the address data latched by the write latch circuit at first to (M−1)-th moments, respectively, in response to the first to (M−1)-th latch control signals, respectively.

7. The address latch according to claim 6 , wherein each of the (M−1) intermediate latch sub-circuit groups comprises a plurality of intermediate latch sub-circuits, and the plurality of intermediate latch sub-circuits are adjacent to each other or not adjacent to each other.

8. The address latch according to claim 6 , wherein each of the N intermediate latch sub-circuits comprises a control terminal, an input terminal, and an output terminal,
the input terminals of the N intermediate latch sub-circuits are connected to the output terminals of the N write latch sub-circuits in one-to-one correspondence manner, and
the control terminals of each of the (M−1) intermediate latch sub-circuit groups are configured to receive a corresponding latch control signal of the first to (M−1)-th latch control signals.

9. The address latch according to claim 6 , wherein the output latch circuit comprises N output latch sub-circuits, the N output latch sub-circuits are connected to the N intermediate latch sub-circuits in one-to-one correspondence manner,
the N output latch sub-circuits are configured to output the address data latched by the N intermediate latch sub-circuits from the address latch at an M-th moment in response to the M-th latch control signal.

10. The address latch according to claim 9 , wherein each of the N output latch sub-circuits comprises a control terminal, an input terminal, and an output terminal,
the input terminals of the N output latch sub-circuits are connected to the output terminals of the N intermediate latch sub-circuits in one-to-one correspondence manner; and
the control terminal of each output latch sub-circuit is configured to receive the M-th latch control signal.

11. The address latch according to claim 9 , wherein each of the N write control sub-circuits is a D flip-flop, each of the N write latch sub-circuits is a D latch, each of the N intermediate latch sub-circuits is a D latch, and each of the N output latch sub-circuits is a D latch.

12. The address latch according to claim 1 , wherein the primary latch control circuit comprises L primary latch control sub-circuits, and each of the L primary latch control sub-circuits comprises a control terminal, an input terminal, and an output terminal,
a control terminal of a 2l−1)-th primary latch control sub-circuit of the L primary latch control sub-circuits is connected to a first control signal line to receive the first control signal, and a control terminal of a 2l-th primary latch control sub-circuit of the L primary latch control sub-circuits is connected to a second control signal line to receive the second control signal, an input terminal of a first primary latch control sub-circuit of the L primary latch control sub-circuits is connected to an enable signal line to receive the latch enable signal, an output terminal of a p-th primary latch control sub-circuit of the L primary latch control sub-circuits is connected to an input terminal of a (p+1)-th primary latch control sub-circuit of

Assignees

• Beijing Boe Technology Dev Co Ltd

Inventors

• Lan Ronghua
• Zhang Junrui
• Zhu Xuehui
• Wang Zhidong
• Zhou Lijia

Classifications

• G11C8/06

  Address interface arrangements, e.g. address buffers · CPC title

• G09G2310/02

  Addressing, scanning or driving the display screen or processing steps related thereto · CPC title

• G11C8/10

  Decoders · CPC title

• G09G3/3677 Primary

  suitable for active matrices only · CPC title

• G09G3/20 Primary

  for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} · CPC title