High instantaneous bandwidth auto-indexing parallelized chaotic waveform data modulator and demodulator with temporal automatic gain control, increased path diversity and sequence lock up prevention

Patent metadata

Field	Value
Publication number	US-11539558-B1
Application number	US-202117374515-A
Country	US
Kind code	B1
Filing date	Jul 13, 2021
Priority date	Jul 13, 2021
Publication date	Dec 27, 2022
Grant date	Dec 27, 2022

Abstract

A transmitter for a chaos communications system employing chaotic symbol modulation that perform auto-indexing, temporal gain control, increased path diversity and sequence lock up prevention. The transmitter includes a symbol mapper that converts a series of information bits to a series of bit symbols, and a chaos modulator providing chaotic spreading modulation of the bit symbols. The chaos modulator includes a plurality of chaos generators, one for each bit symbol, providing a chaos sequence for the bit symbols. Each chaos modulator includes a RAM/ROM that provides auto-indexing where a chaos sequence output from the RAM/ROM is fed back to an input of the RAM/ROM from which a chaos sequence at a next address in the RAM/ROM is selected as the output of the modulator.

First claim

What is claimed is:

1. A transmitter for a chaos communications system, said transmitter comprising:
a symbol mapper that converts a series of information bits to a series of bit symbols; and
at least one chaos generator providing a chaos sequence for each bit symbol, said at least one chaos modulator having a RAM/ROM that provides auto-indexing where a chaos sequence output from the RAM/ROM is fed back to an input of the RAM/ROM from which a chaos sequence at a next address in the RAM/ROM is selected as the output of the generator.

2. The transmitter according to claim 1 wherein the at least one chaos generator is a plurality of chaos generators.

3. The transmitter according to claim 1 wherein the RAM/ROM includes an additional column at the end of each RAM address that prevents chaos sequence lock up.

4. The transmitter according to claim 1 wherein the at least one chaos generator converts floating-point chaos sequences to fixed-point chaos sequences.

5. The transmitter according to claim 1 wherein the auto-indexing is governed by an initial state set by a RESET signal.

6. The transmitter according to claim 1 wherein the auto-indexing is performed with multiple start phases.

7. The transmitter according to claim 1 wherein the transmitter further includes a temporal automatic gain controller (AGC) that controls the gain of the chaos sequence for transmission.

8. A transmitter for a chaos communications system, said transmitter comprising:
a symbol mapper that converts a series of information bits to a series of bit symbols; and
at least one chaos generator providing a chaos sequence for each bit symbol, said at least one chaos modulator including a RAM/ROM that provides auto-indexing where a chaos sequence output from the RAM/ROM is fed back to an input of the RAM/ROM from which a chaos sequence at a next address in the RAM/ROM is selected as the output of the generator, wherein the RAM/ROM includes an additional column to the end of each RAM address that prevents chaos sequence lock up, the at least one chaos generator converts floating-point chaos sequences to fixed-point chaos sequences, and the transmitter further includes a temporal automatic gain controller (AGC) that controls the gain of the chaos sequence for transmission.

9. The transmitter according to claim 8 wherein the at least one chaos generator is a plurality of chaos generators.

10. The transmitter according to claim 8 wherein the auto-indexing is governed by an initial state set by a RESET signal.

11. The transmitter according to claim 8 wherein the auto-indexing is performed with multiple start phases.

12. A method for communications comprising:
converting a series of information bits to a series of bit symbols; and
generating a chaotic sequence for transmission for each bit symbol that includes auto-indexing where a chaos sequence output from a RAM/ROM is fed back to an input of the RAM/ROM from which a chaos sequence at a next address in the RAM/ROM is selected as the next chaotic sequence for the bit symbol.

13. The method according to claim 12 wherein the RAM/ROM includes a shadow register that prevents chaos sequence lock up.

14. The method according to claim 12 further comprising converting floating-point chaos sequences to fixed-point chaos sequences.

15. The method according to claim 12 further comprising providing temporal automatic gain control (AGC) to controls the gain of the chaos sequence.

16. The method according to claim 12 wherein the auto-indexing is governed by an initial state set by a RESET signal.

17. The method according to claim 12 wherein the auto-indexing is performed with multiple start phases.

Assignees

• Northrop Grumman Systems Corp

Inventors

• Pandya Ameesh N
• Azizian Armin
• Walker Christopher W
• Marquez Marlon

Classifications

• H04B2001/6904

  using code hopping · CPC title

• H04L27/001 Primary

  using chaotic signals (for secret or secure communication H04L9/001) · CPC title

• H04J13/0018

  Chaotic · CPC title

• H04L9/001

  using chaotic signals · CPC title

• H04B1/69

  Spread spectrum techniques · CPC title