Physically unclonable function with precharge through bit lines

Patent metadata

Field	Value
Publication number	US-11539536-B2
Application number	US-202016850606-A
Country	US
Kind code	B2
Filing date	Apr 16, 2020
Priority date	Apr 16, 2020
Publication date	Dec 27, 2022
Grant date	Dec 27, 2022

Abstract

A physically unclonable function (PUF) includes a bit cell that includes a latch and a switch to selectively couple the latch to a supply voltage node. A first transmission gate couples a first bit line to a first internal node of the latch and a second transmission gate couples a second bit line to a second internal node of the latch. A digital to analog converter (DAC) circuit is selectively coupled to the first internal node through the first bit line and the first transmission gate and to the second internal node through the second bit line and the second transmission gate, to thereby precharge the latch before the first bit cell is read. The latch regenerates responsive to the switch being closed to connect the latch to the supply voltage node. The first and second bit lines are used to read the regenerated value of the latch.

First claim

What is claimed is:

1. A physically unclonable function (PUF), comprising:
a first bit cell including,
a latch;
a switch to selectively couple the latch to a supply voltage node;
a first transmission gate coupled between a first bit line and a first internal node of the latch and a second transmission gate coupled between a second bit line and a second internal node of the latch;

a digital to analog converter (DAC) circuit having a first DAC output selectively coupled to the first internal node through the first bit line and the first transmission gate and having a second DAC output selectively coupled to the second internal node through the second bit line and the second transmission gate, to precharge the latch before the first bit cell is read, the latch being precharged with the latch decoupled from the supply voltage node;
wherein after the precharge of the latch, the first and second bit lines are disconnected from the first and second internal nodes by turning off the first and second transmission gates and the first bit line and the second bit line are precharged to a predetermined voltage level;
wherein after the first and second bit lines are precharged to the predetermined voltage level, the latch is coupled to the supply voltage node to cause the first bit cell to regenerate; and
wherein after the first bit cell regenerates, the first and second internal nodes are respectively coupled to the first and second bit lines to read a value of the latch.

2. The physically unclonable function as recited in claim 1 wherein the latch is a four transistor latch.

3. The physically unclonable function as recited in claim 1 wherein the supply voltage node is a ground node.

4. The physically unclonable function as recited in claim 1 further comprising:
a bit line termination circuit selectively coupling the first and second bit lines to the DAC circuit according to a control signal.

5. The physically unclonable function as recited in claim 4 , wherein the bit line termination circuit further comprises:
a first termination switch to selectively set the first bit line to a predetermined voltage and a second termination switch to selectively set the second bit line to the predetermined voltage.

6. The physically unclonable function as recited in claim 4 , wherein the bit line termination circuit further comprises:
a tristate driver coupled to the first bit line, the tristate driver to supply a data out signal corresponding to a read value of the latch.

7. The physically unclonable function as recited in claim 4 , further comprising:
a first PUF page including,
an array of bit cells including the first bit cell;
a first plurality of the array of bit cells disposed in a first column of the array, each bit cell in the first column being coupled to the first and second bit lines, the first plurality of the array of bit cells including the first bit cell; and
a second plurality of the array of bit cells in a first row of the array, the first row including the first bit cell, each bit cell in the first row being coupled to a first row signal that selectively activates the first and second transmission gates and a second row signal that selectively controls the switch to couple the latch to the supply voltage node.

8. The physically unclonable function as recited in claim 7 further comprising:
a plurality of pairs of bit lines coupled to the array of bit cells;
wherein each of the second plurality of the array of bit cells in the first row is coupled to a different pair of the plurality of pairs of bit lines; and
the DAC circuit is coupled to the plurality of pairs of bit lines.

9. The physically unclonable function as recited in claim 7 further comprising:
a plurality of PUF pages including the first PUF page; and
a memory controller to control access to bit cells of the plurality of PUF pages.

10. The physically unclonable function as recited in claim 1 wherein,
in a disabled state, the first bit cell is placed in a high impedance state by disconnecting the supply voltage node using the switch and the first and second internal nodes are coupled to the first and second bit lines through the first and second transmission gates to thereby couple the first and second internal nodes to a predetermined logic state.

11. A method for performing a read operation of a bit cell in a physically unclonable function (PUF), the read operation comprising:
precharging a latch in the bit cell with the latch decoupled from a supply voltage node, the precharging including coupling a first output of a digital to analog converter (DAC) circuit to a first internal node in a latch of the bit cell through a first bit line and a first transmission gate and coupling a second output of the DAC circuit to a second internal node in the latch through a second bit line and a second transmission gate;
disconnecting the first and second bit lines from the first and second internal nodes after allowing for a settling time for the precharge of the bit cell;
precharging the first bit line and the second bit line to a predetermined voltage level after the settling time with the first and second bit lines disconnected from the first and second internal nodes;
after precharging the first and second bit lines, coupling the latch to the supply voltage node to cause the bit cell to regenerate; and
reading a value of the latch using at least one of the first and second bit lines.

12. The method as recited in claim 11 further comprising disconnecting the DAC circuit from the first and second bit lines before precharging the first and second bit lines.

13. The method as recited in claim 12 further comprising disabling the DAC after disconnecting the DAC from the first and second bit lines.

14. The method as recited in claim 11 wherein the supply voltage node is a ground node.

15. The method as recited in claim 11 , wherein the predetermined voltage level is ground.

16. The method as recited in claim 11 , further comprising:
supplying a data out signal corresponding to the value of the latch to a tristate driver from at least one of the first and second bit lines; and
supplying the data out signal from the tristate driver.

17. The method as recited in claim 11 further comprising:
in a disabled state, disconnecting the latch in the bit cell from the supply voltage node, and coupling the first and second internal nodes to the first and second bit lines through the first and second transmission gates, the first and second bit lines being coupled to a voltage node having a predetermined voltage in the disabled state.

18. A method, comprising:
precharging a latch in a bit cell of a physically unclonable function (PUF) using a differential voltage applied to first and second bit lines with the latch decoupled from a supply voltage node;
after precharging the latch, precharging the first and second bit lines while the first and second bit lines are disconnected from the latch;
causing the latch to regenerate by coupling the latch to the supply voltage node; and
reading a value of the latch using at least one of the first and second bit lines.

19. The method as recited in claim 18 further comprising:
in a disabled state, disconnecting the latch in the bit cell from the supply voltage node and coupling first and second internal nodes in the latch to the first and second bit lines through first and second transmission gates, the first and second bit lines being coupled to a predetermined voltage in the disabled state.

Assignees

• Silicon Lab Inc

Inventors

• Sonntag Jeffrey L
• Osman Hatem M
• Yuan Gang

Classifications

• G11C7/12

  Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines · CPC title

• G11C5/147

  Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops (G11C5/141 takes precedence) · CPC title

• G11C11/4094

  Bit-line management or control circuits · CPC title

• G06M1/272

  using photoelectric means · CPC title

• G11C11/4074

  Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits · CPC title